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/*  cpu_asm.s   1.1 - 95/12/04
 *
 *  This file contains the assembly code for the PowerPC implementation
 *  of RTEMS.
 *
 *  Author:     Andrew Bray 
 *
 *  COPYRIGHT (c) 1995 by i-cubed ltd.
 *
 *  To anyone who acknowledges that this file is provided "AS IS"
 *  without any express or implied warranty:
 *      permission to use, copy, modify, and distribute this file
 *      for any purpose is hereby granted without fee, provided that
 *      the above copyright notice and this notice appears in all
 *      copies, and that the name of i-cubed limited not be used in
 *      advertising or publicity pertaining to distribution of the
 *      software without specific, written prior permission.
 *      i-cubed limited makes no representations about the suitability
 *      of this software for any purpose.
 *
 *  Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
 *
 *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *  Copyright assigned to U.S. Government, 1994.
 *
 *  The license and distribution terms for this file may in
 *  the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: cpu_asm.S,v 1.2 2001-09-27 11:59:29 chris Exp $
 */
 
#include 
 
/*
 * Offsets for various Contexts
 */
        .set    GP_1, 0
        .set    GP_2, (GP_1 + 4)
        .set    GP_13, (GP_2 + 4)
        .set    GP_14, (GP_13 + 4)
 
        .set    GP_15, (GP_14 + 4)
        .set    GP_16, (GP_15 + 4)
        .set    GP_17, (GP_16 + 4)
        .set    GP_18, (GP_17 + 4)
 
        .set    GP_19, (GP_18 + 4)
        .set    GP_20, (GP_19 + 4)
        .set    GP_21, (GP_20 + 4)
        .set    GP_22, (GP_21 + 4)
 
        .set    GP_23, (GP_22 + 4)
        .set    GP_24, (GP_23 + 4)
        .set    GP_25, (GP_24 + 4)
        .set    GP_26, (GP_25 + 4)
 
        .set    GP_27, (GP_26 + 4)
        .set    GP_28, (GP_27 + 4)
        .set    GP_29, (GP_28 + 4)
        .set    GP_30, (GP_29 + 4)
 
        .set    GP_31, (GP_30 + 4)
        .set    GP_CR, (GP_31 + 4)
        .set    GP_PC, (GP_CR + 4)
        .set    GP_MSR, (GP_PC + 4)
 
#if (PPC_HAS_DOUBLE == 1)
        .set    FP_0, 0
        .set    FP_1, (FP_0 + 8)
        .set    FP_2, (FP_1 + 8)
        .set    FP_3, (FP_2 + 8)
        .set    FP_4, (FP_3 + 8)
        .set    FP_5, (FP_4 + 8)
        .set    FP_6, (FP_5 + 8)
        .set    FP_7, (FP_6 + 8)
        .set    FP_8, (FP_7 + 8)
        .set    FP_9, (FP_8 + 8)
        .set    FP_10, (FP_9 + 8)
        .set    FP_11, (FP_10 + 8)
        .set    FP_12, (FP_11 + 8)
        .set    FP_13, (FP_12 + 8)
        .set    FP_14, (FP_13 + 8)
        .set    FP_15, (FP_14 + 8)
        .set    FP_16, (FP_15 + 8)
        .set    FP_17, (FP_16 + 8)
        .set    FP_18, (FP_17 + 8)
        .set    FP_19, (FP_18 + 8)
        .set    FP_20, (FP_19 + 8)
        .set    FP_21, (FP_20 + 8)
        .set    FP_22, (FP_21 + 8)
        .set    FP_23, (FP_22 + 8)
        .set    FP_24, (FP_23 + 8)
        .set    FP_25, (FP_24 + 8)
        .set    FP_26, (FP_25 + 8)
        .set    FP_27, (FP_26 + 8)
        .set    FP_28, (FP_27 + 8)
        .set    FP_29, (FP_28 + 8)
        .set    FP_30, (FP_29 + 8)
        .set    FP_31, (FP_30 + 8)
        .set    FP_FPSCR, (FP_31 + 8)
#else
        .set    FP_0, 0
        .set    FP_1, (FP_0 + 4)
        .set    FP_2, (FP_1 + 4)
        .set    FP_3, (FP_2 + 4)
        .set    FP_4, (FP_3 + 4)
        .set    FP_5, (FP_4 + 4)
        .set    FP_6, (FP_5 + 4)
        .set    FP_7, (FP_6 + 4)
        .set    FP_8, (FP_7 + 4)
        .set    FP_9, (FP_8 + 4)
        .set    FP_10, (FP_9 + 4)
        .set    FP_11, (FP_10 + 4)
        .set    FP_12, (FP_11 + 4)
        .set    FP_13, (FP_12 + 4)
        .set    FP_14, (FP_13 + 4)
        .set    FP_15, (FP_14 + 4)
        .set    FP_16, (FP_15 + 4)
        .set    FP_17, (FP_16 + 4)
        .set    FP_18, (FP_17 + 4)
        .set    FP_19, (FP_18 + 4)
        .set    FP_20, (FP_19 + 4)
        .set    FP_21, (FP_20 + 4)
        .set    FP_22, (FP_21 + 4)
        .set    FP_23, (FP_22 + 4)
        .set    FP_24, (FP_23 + 4)
        .set    FP_25, (FP_24 + 4)
        .set    FP_26, (FP_25 + 4)
        .set    FP_27, (FP_26 + 4)
        .set    FP_28, (FP_27 + 4)
        .set    FP_29, (FP_28 + 4)
        .set    FP_30, (FP_29 + 4)
        .set    FP_31, (FP_30 + 4)
        .set    FP_FPSCR, (FP_31 + 4)
#endif
 
        .set    IP_LINK, 0
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
        .set    IP_0, (IP_LINK + 56)
#else
        .set    IP_0, (IP_LINK + 8)
#endif
        .set    IP_2, (IP_0 + 4)
 
        .set    IP_3, (IP_2 + 4)
        .set    IP_4, (IP_3 + 4)
        .set    IP_5, (IP_4 + 4)
        .set    IP_6, (IP_5 + 4)
 
        .set    IP_7, (IP_6 + 4)
        .set    IP_8, (IP_7 + 4)
        .set    IP_9, (IP_8 + 4)
        .set    IP_10, (IP_9 + 4)
 
        .set    IP_11, (IP_10 + 4)
        .set    IP_12, (IP_11 + 4)
        .set    IP_13, (IP_12 + 4)
        .set    IP_28, (IP_13 + 4)
 
        .set    IP_29, (IP_28 + 4)
        .set    IP_30, (IP_29 + 4)
        .set    IP_31, (IP_30 + 4)
        .set    IP_CR, (IP_31 + 4)
 
        .set    IP_CTR, (IP_CR + 4)
        .set    IP_XER, (IP_CTR + 4)
        .set    IP_LR, (IP_XER + 4)
        .set    IP_PC, (IP_LR + 4)
 
        .set    IP_MSR, (IP_PC + 4)
        .set    IP_END, (IP_MSR + 16)
 
        /* _CPU_IRQ_info offsets */
 
        /* These must be in this order */
        .set    Nest_level, 0
        .set    Disable_level, 4
        .set    Vector_table, 8
        .set    Stack, 12
#if (PPC_ABI == PPC_ABI_POWEROPEN)
        .set    Dispatch_r2, 16
        .set    Switch_necessary, 20
#else
        .set    Default_r2, 16
#if (PPC_ABI != PPC_ABI_GCC27)
        .set    Default_r13, 20
        .set    Switch_necessary, 24
#else
        .set    Switch_necessary, 20
#endif
#endif
        .set    Signal, Switch_necessary + 4
        .set    msr_initial, Signal + 4
 
        BEGIN_CODE
/*
 *  _CPU_Context_save_fp_context
 *
 *  This routine is responsible for saving the FP context
 *  at *fp_context_ptr.  If the point to load the FP context
 *  from is changed then the pointer is modified by this routine.
 *
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
 *  the ** and a similarly named routine in this file is passed something
 *  like a (Context_Control_fp *).  The general rule on making this decision
 *  is to avoid writing assembly language.
 */
 
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_CPU_Context_save_fp)
PROC (_CPU_Context_save_fp):
#if (PPC_HAS_FPU == 1)
        lwz     r3, 0(r3)
#if (PPC_HAS_DOUBLE == 1)
        stfd    f0, FP_0(r3)
        stfd    f1, FP_1(r3)
        stfd    f2, FP_2(r3)
        stfd    f3, FP_3(r3)
        stfd    f4, FP_4(r3)
        stfd    f5, FP_5(r3)
        stfd    f6, FP_6(r3)
        stfd    f7, FP_7(r3)
        stfd    f8, FP_8(r3)
        stfd    f9, FP_9(r3)
        stfd    f10, FP_10(r3)
        stfd    f11, FP_11(r3)
        stfd    f12, FP_12(r3)
        stfd    f13, FP_13(r3)
        stfd    f14, FP_14(r3)
        stfd    f15, FP_15(r3)
        stfd    f16, FP_16(r3)
        stfd    f17, FP_17(r3)
        stfd    f18, FP_18(r3)
        stfd    f19, FP_19(r3)
        stfd    f20, FP_20(r3)
        stfd    f21, FP_21(r3)
        stfd    f22, FP_22(r3)
        stfd    f23, FP_23(r3)
        stfd    f24, FP_24(r3)
        stfd    f25, FP_25(r3)
        stfd    f26, FP_26(r3)
        stfd    f27, FP_27(r3)
        stfd    f28, FP_28(r3)
        stfd    f29, FP_29(r3)
        stfd    f30, FP_30(r3)
        stfd    f31, FP_31(r3)
        mffs    f2
        stfd    f2, FP_FPSCR(r3)
#else
        stfs    f0, FP_0(r3)
        stfs    f1, FP_1(r3)
        stfs    f2, FP_2(r3)
        stfs    f3, FP_3(r3)
        stfs    f4, FP_4(r3)
        stfs    f5, FP_5(r3)
        stfs    f6, FP_6(r3)
        stfs    f7, FP_7(r3)
        stfs    f8, FP_8(r3)
        stfs    f9, FP_9(r3)
        stfs    f10, FP_10(r3)
        stfs    f11, FP_11(r3)
        stfs    f12, FP_12(r3)
        stfs    f13, FP_13(r3)
        stfs    f14, FP_14(r3)
        stfs    f15, FP_15(r3)
        stfs    f16, FP_16(r3)
        stfs    f17, FP_17(r3)
        stfs    f18, FP_18(r3)
        stfs    f19, FP_19(r3)
        stfs    f20, FP_20(r3)
        stfs    f21, FP_21(r3)
        stfs    f22, FP_22(r3)
        stfs    f23, FP_23(r3)
        stfs    f24, FP_24(r3)
        stfs    f25, FP_25(r3)
        stfs    f26, FP_26(r3)
        stfs    f27, FP_27(r3)
        stfs    f28, FP_28(r3)
        stfs    f29, FP_29(r3)
        stfs    f30, FP_30(r3)
        stfs    f31, FP_31(r3)
        mffs    f2
        stfs    f2, FP_FPSCR(r3)
#endif
#endif
        blr
 
/*
 *  _CPU_Context_restore_fp_context
 *
 *  This routine is responsible for restoring the FP context
 *  at *fp_context_ptr.  If the point to load the FP context
 *  from is changed then the pointer is modified by this routine.
 *
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
 *  the ** and a similarly named routine in this file is passed something
 *  like a (Context_Control_fp *).  The general rule on making this decision
 *  is to avoid writing assembly language.
 */
 
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_CPU_Context_restore_fp)
PROC (_CPU_Context_restore_fp):
#if (PPC_HAS_FPU == 1)
        lwz     r3, 0(r3)
#if (PPC_HAS_DOUBLE == 1)
        lfd     f2, FP_FPSCR(r3)
        mtfsf   255, f2
        lfd     f0, FP_0(r3)
        lfd     f1, FP_1(r3)
        lfd     f2, FP_2(r3)
        lfd     f3, FP_3(r3)
        lfd     f4, FP_4(r3)
        lfd     f5, FP_5(r3)
        lfd     f6, FP_6(r3)
        lfd     f7, FP_7(r3)
        lfd     f8, FP_8(r3)
        lfd     f9, FP_9(r3)
        lfd     f10, FP_10(r3)
        lfd     f11, FP_11(r3)
        lfd     f12, FP_12(r3)
        lfd     f13, FP_13(r3)
        lfd     f14, FP_14(r3)
        lfd     f15, FP_15(r3)
        lfd     f16, FP_16(r3)
        lfd     f17, FP_17(r3)
        lfd     f18, FP_18(r3)
        lfd     f19, FP_19(r3)
        lfd     f20, FP_20(r3)
        lfd     f21, FP_21(r3)
        lfd     f22, FP_22(r3)
        lfd     f23, FP_23(r3)
        lfd     f24, FP_24(r3)
        lfd     f25, FP_25(r3)
        lfd     f26, FP_26(r3)
        lfd     f27, FP_27(r3)
        lfd     f28, FP_28(r3)
        lfd     f29, FP_29(r3)
        lfd     f30, FP_30(r3)
        lfd     f31, FP_31(r3)
#else
        lfs     f2, FP_FPSCR(r3)
        mtfsf   255, f2
        lfs     f0, FP_0(r3)
        lfs     f1, FP_1(r3)
        lfs     f2, FP_2(r3)
        lfs     f3, FP_3(r3)
        lfs     f4, FP_4(r3)
        lfs     f5, FP_5(r3)
        lfs     f6, FP_6(r3)
        lfs     f7, FP_7(r3)
        lfs     f8, FP_8(r3)
        lfs     f9, FP_9(r3)
        lfs     f10, FP_10(r3)
        lfs     f11, FP_11(r3)
        lfs     f12, FP_12(r3)
        lfs     f13, FP_13(r3)
        lfs     f14, FP_14(r3)
        lfs     f15, FP_15(r3)
        lfs     f16, FP_16(r3)
        lfs     f17, FP_17(r3)
        lfs     f18, FP_18(r3)
        lfs     f19, FP_19(r3)
        lfs     f20, FP_20(r3)
        lfs     f21, FP_21(r3)
        lfs     f22, FP_22(r3)
        lfs     f23, FP_23(r3)
        lfs     f24, FP_24(r3)
        lfs     f25, FP_25(r3)
        lfs     f26, FP_26(r3)
        lfs     f27, FP_27(r3)
        lfs     f28, FP_28(r3)
        lfs     f29, FP_29(r3)
        lfs     f30, FP_30(r3)
        lfs     f31, FP_31(r3)
#endif
#endif
        blr
 
 
/*  _CPU_Context_switch
 *
 *  This routine performs a normal non-FP context switch.
 */
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_CPU_Context_switch)
PROC (_CPU_Context_switch):
        sync
        isync
#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */
        stw     r1, GP_1(r3)
        lwz     r1, GP_1(r4)
        stw     r2, GP_2(r3)
        lwz     r2, GP_2(r4)
#if (PPC_USE_MULTIPLE == 1)
        stmw    r13, GP_13(r3)
        lmw     r13, GP_13(r4)
#else
        stw     r13, GP_13(r3)
        lwz     r13, GP_13(r4)
        stw     r14, GP_14(r3)
        lwz     r14, GP_14(r4)
        stw     r15, GP_15(r3)
        lwz     r15, GP_15(r4)
        stw     r16, GP_16(r3)
        lwz     r16, GP_16(r4)
        stw     r17, GP_17(r3)
        lwz     r17, GP_17(r4)
        stw     r18, GP_18(r3)
        lwz     r18, GP_18(r4)
        stw     r19, GP_19(r3)
        lwz     r19, GP_19(r4)
        stw     r20, GP_20(r3)
        lwz     r20, GP_20(r4)
        stw     r21, GP_21(r3)
        lwz     r21, GP_21(r4)
        stw     r22, GP_22(r3)
        lwz     r22, GP_22(r4)
        stw     r23, GP_23(r3)
        lwz     r23, GP_23(r4)
        stw     r24, GP_24(r3)
        lwz     r24, GP_24(r4)
        stw     r25, GP_25(r3)
        lwz     r25, GP_25(r4)
        stw     r26, GP_26(r3)
        lwz     r26, GP_26(r4)
        stw     r27, GP_27(r3)
        lwz     r27, GP_27(r4)
        stw     r28, GP_28(r3)
        lwz     r28, GP_28(r4)
        stw     r29, GP_29(r3)
        lwz     r29, GP_29(r4)
        stw     r30, GP_30(r3)
        lwz     r30, GP_30(r4)
        stw     r31, GP_31(r3)
        lwz     r31, GP_31(r4)
#endif
        mfcr    r5
        stw     r5, GP_CR(r3)
        lwz     r5, GP_CR(r4)
        mflr    r6
        mtcrf   255, r5
        stw     r6, GP_PC(r3)
        lwz     r6, GP_PC(r4)
        mfmsr   r7
        mtlr    r6
        stw     r7, GP_MSR(r3)
        lwz     r7, GP_MSR(r4)
        mtmsr   r7
#endif
#if (PPC_CACHE_ALIGNMENT == 16)
        /* This assumes that all the registers are in the given order */
        li      r5, 16
        addi    r3,r3,-4
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r1, GP_1+4(r3)
        stw     r2, GP_2+4(r3)
#if (PPC_USE_MULTIPLE == 1)
        addi    r3, r3, GP_14+4
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
 
        addi    r3, r3, GP_18-GP_14
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        addi    r3, r3, GP_22-GP_18
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        addi    r3, r3, GP_26-GP_22
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stmw    r13, GP_13-GP_26(r3)
#else
        stw     r13, GP_13+4(r3)
        stwu    r14, GP_14+4(r3)
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r15, GP_15-GP_14(r3)
        stw     r16, GP_16-GP_14(r3)
        stw     r17, GP_17-GP_14(r3)
        stwu    r18, GP_18-GP_14(r3)
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r19, GP_19-GP_18(r3)
        stw     r20, GP_20-GP_18(r3)
        stw     r21, GP_21-GP_18(r3)
        stwu    r22, GP_22-GP_18(r3)
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r23, GP_23-GP_22(r3)
        stw     r24, GP_24-GP_22(r3)
        stw     r25, GP_25-GP_22(r3)
        stwu    r26, GP_26-GP_22(r3)
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r27, GP_27-GP_26(r3)
        stw     r28, GP_28-GP_26(r3)
        stw     r29, GP_29-GP_26(r3)
        stw     r30, GP_30-GP_26(r3)
        stw     r31, GP_31-GP_26(r3)
#endif
#if ( PPC_USE_DATA_CACHE )
        dcbt    r0, r4
#endif
        mfcr    r6
        stw     r6, GP_CR-GP_26(r3)
        mflr    r7
        stw     r7, GP_PC-GP_26(r3)
        mfmsr   r8
        stw     r8, GP_MSR-GP_26(r3)
 
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r1, GP_1(r4)
        lwz     r2, GP_2(r4)
#if (PPC_USE_MULTIPLE == 1)
        addi    r4, r4, GP_15
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        addi    r4, r4, GP_19-GP_15
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        addi    r4, r4, GP_23-GP_19
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        addi    r4, r4, GP_27-GP_23
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lmw     r13, GP_13-GP_27(r4)
#else
        lwz     r13, GP_13(r4)
        lwz     r14, GP_14(r4)
        lwzu    r15, GP_15(r4)
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r16, GP_16-GP_15(r4)
        lwz     r17, GP_17-GP_15(r4)
        lwz     r18, GP_18-GP_15(r4)
        lwzu    r19, GP_19-GP_15(r4)
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r20, GP_20-GP_19(r4)
        lwz     r21, GP_21-GP_19(r4)
        lwz     r22, GP_22-GP_19(r4)
        lwzu    r23, GP_23-GP_19(r4)
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r24, GP_24-GP_23(r4)
        lwz     r25, GP_25-GP_23(r4)
        lwz     r26, GP_26-GP_23(r4)
        lwzu    r27, GP_27-GP_23(r4)
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r28, GP_28-GP_27(r4)
        lwz     r29, GP_29-GP_27(r4)
        lwz     r30, GP_30-GP_27(r4)
        lwz     r31, GP_31-GP_27(r4)
#endif
        lwz     r6, GP_CR-GP_27(r4)
        lwz     r7, GP_PC-GP_27(r4)
        lwz     r8, GP_MSR-GP_27(r4)
        mtcrf   255, r6
        mtlr    r7
        mtmsr   r8
#endif
#if (PPC_CACHE_ALIGNMENT == 32)
        /* This assumes that all the registers are in the given order */
        li      r5, 32
        addi    r3,r3,-4
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r1, GP_1+4(r3)
        stw     r2, GP_2+4(r3)
#if (PPC_USE_MULTIPLE == 1)
        addi    r3, r3, GP_18+4
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stmw    r13, GP_13-GP_18(r3)
#else
        stw     r13, GP_13+4(r3)
        stw     r14, GP_14+4(r3)
        stw     r15, GP_15+4(r3)
        stw     r16, GP_16+4(r3)
        stw     r17, GP_17+4(r3)
        stwu    r18, GP_18+4(r3)
#if ( PPC_USE_DATA_CACHE )
        dcbz    r5, r3
#endif
        stw     r19, GP_19-GP_18(r3)
        stw     r20, GP_20-GP_18(r3)
        stw     r21, GP_21-GP_18(r3)
        stw     r22, GP_22-GP_18(r3)
        stw     r23, GP_23-GP_18(r3)
        stw     r24, GP_24-GP_18(r3)
        stw     r25, GP_25-GP_18(r3)
        stw     r26, GP_26-GP_18(r3)
        stw     r27, GP_27-GP_18(r3)
        stw     r28, GP_28-GP_18(r3)
        stw     r29, GP_29-GP_18(r3)
        stw     r30, GP_30-GP_18(r3)
        stw     r31, GP_31-GP_18(r3)
#endif
#if ( PPC_USE_DATA_CACHE )
        dcbt    r0, r4
#endif
        mfcr    r6
        stw     r6, GP_CR-GP_18(r3)
        mflr    r7
        stw     r7, GP_PC-GP_18(r3)
        mfmsr   r8
        stw     r8, GP_MSR-GP_18(r3)
 
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r1, GP_1(r4)
        lwz     r2, GP_2(r4)
#if (PPC_USE_MULTIPLE == 1)
        addi    r4, r4, GP_19
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lmw     r13, GP_13-GP_19(r4)
#else
        lwz     r13, GP_13(r4)
        lwz     r14, GP_14(r4)
        lwz     r15, GP_15(r4)
        lwz     r16, GP_16(r4)
        lwz     r17, GP_17(r4)
        lwz     r18, GP_18(r4)
        lwzu    r19, GP_19(r4)
#if ( PPC_USE_DATA_CACHE )
        dcbt    r5, r4
#endif
        lwz     r20, GP_20-GP_19(r4)
        lwz     r21, GP_21-GP_19(r4)
        lwz     r22, GP_22-GP_19(r4)
        lwz     r23, GP_23-GP_19(r4)
        lwz     r24, GP_24-GP_19(r4)
        lwz     r25, GP_25-GP_19(r4)
        lwz     r26, GP_26-GP_19(r4)
        lwz     r27, GP_27-GP_19(r4)
        lwz     r28, GP_28-GP_19(r4)
        lwz     r29, GP_29-GP_19(r4)
        lwz     r30, GP_30-GP_19(r4)
        lwz     r31, GP_31-GP_19(r4)
#endif
        lwz     r6, GP_CR-GP_19(r4)
        lwz     r7, GP_PC-GP_19(r4)
        lwz     r8, GP_MSR-GP_19(r4)
        mtcrf   255, r6
        mtlr    r7
        mtmsr   r8
#endif
        blr
 
/*
 *  _CPU_Context_restore
 *
 *  This routine is generallu used only to restart self in an
 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
 *
 *  NOTE: May be unnecessary to reload some registers.
 */
/*
 * ACB: Don't worry about cache optimisation here - this is not THAT critical.
 */
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_CPU_Context_restore)
PROC (_CPU_Context_restore):
        lwz     r5, GP_CR(r3)
        lwz     r6, GP_PC(r3)
        lwz     r7, GP_MSR(r3)
        mtcrf   255, r5
        mtlr    r6
        mtmsr   r7
        lwz     r1, GP_1(r3)
        lwz     r2, GP_2(r3)
#if (PPC_USE_MULTIPLE == 1)
        lmw     r13, GP_13(r3)
#else
        lwz     r13, GP_13(r3)
        lwz     r14, GP_14(r3)
        lwz     r15, GP_15(r3)
        lwz     r16, GP_16(r3)
        lwz     r17, GP_17(r3)
        lwz     r18, GP_18(r3)
        lwz     r19, GP_19(r3)
        lwz     r20, GP_20(r3)
        lwz     r21, GP_21(r3)
        lwz     r22, GP_22(r3)
        lwz     r23, GP_23(r3)
        lwz     r24, GP_24(r3)
        lwz     r25, GP_25(r3)
        lwz     r26, GP_26(r3)
        lwz     r27, GP_27(r3)
        lwz     r28, GP_28(r3)
        lwz     r29, GP_29(r3)
        lwz     r30, GP_30(r3)
        lwz     r31, GP_31(r3)
#endif
 
        blr
 
/*  Individual interrupt prologues look like this:
 * #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
 * #if (PPC_HAS_FPU)
 *      stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
 * #else
 *      stwu    r1, -(20*4 + IP_END)(r1)
 * #endif
 * #else
 *      stwu    r1, -(IP_END)(r1)
 * #endif
 *      stw     r0, IP_0(r1)
 *
 *      li      r0, vectornum
 *      b       PROC (_ISR_Handler{,C})
 */
 
/*  void __ISR_Handler()
 *
 *  This routine provides the RTEMS interrupt management.
 *  The vector number is in r0. R0 has already been stacked.
 *
 */
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_ISR_Handler)
PROC (_ISR_Handler):
#define LABEL(x)        x
/*  XXX ??
#define MTSAVE(x)       mtspr   sprg0, x
#define MFSAVE(x)       mfspr   x, sprg0
*/
#define MTPC(x)         mtspr   srr0, x
#define MFPC(x)         mfspr   x, srr0
#define MTMSR(x)        mtspr   srr1, x
#define MFMSR(x)        mfspr   x, srr1
 
        #include        "irq_stub.S"
        rfi
 
#if (PPC_HAS_RFCI == 1)
/*  void __ISR_HandlerC()
 *
 *  This routine provides the RTEMS interrupt management.
 *  For critical interrupts
 *
 */
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
        PUBLIC_PROC (_ISR_HandlerC)
PROC (_ISR_HandlerC):
#undef  LABEL
#undef  MTSAVE
#undef  MFSAVE
#undef  MTPC
#undef  MFPC
#undef  MTMSR
#undef  MFMSR
#define LABEL(x)        x##_C
/* XXX??
#define MTSAVE(x)       mtspr   sprg1, x
#define MFSAVE(x)       mfspr   x, sprg1
*/
#define MTPC(x)         mtspr   srr2, x
#define MFPC(x)         mfspr   x, srr2
#define MTMSR(x)        mtspr   srr3, x
#define MFMSR(x)        mfspr   x, srr3
        #include        "irq_stub.S"
        rfci
#endif
 
/*  PowerOpen descriptors for indirect function calls.
 */
 
#if (PPC_ABI == PPC_ABI_POWEROPEN)
        DESCRIPTOR (_CPU_Context_save_fp)
        DESCRIPTOR (_CPU_Context_restore_fp)
        DESCRIPTOR (_CPU_Context_switch)
        DESCRIPTOR (_CPU_Context_restore)
        DESCRIPTOR (_ISR_Handler)
#if (PPC_HAS_RFCI == 1)
        DESCRIPTOR (_ISR_HandlerC)
#endif
#endif

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [old_exception_processing/] [cpu_asm.S] - Blame information for rev 773

Line No.	Rev	Author	Line
1	30	unneback
2			`/* cpu_asm.s 1.1 - 95/12/04`
3			`*`
4			`* This file contains the assembly code for the PowerPC implementation`
5			`* of RTEMS.`
6			`*`
7			`* Author: Andrew Bray`
8			`*`
9			`* COPYRIGHT (c) 1995 by i-cubed ltd.`
10			`*`
11			`* To anyone who acknowledges that this file is provided "AS IS"`
12			`* without any express or implied warranty:`
13			`* permission to use, copy, modify, and distribute this file`
14			`* for any purpose is hereby granted without fee, provided that`
15			`* the above copyright notice and this notice appears in all`
16			`* copies, and that the name of i-cubed limited not be used in`
17			`* advertising or publicity pertaining to distribution of the`
18			`* software without specific, written prior permission.`
19			`* i-cubed limited makes no representations about the suitability`
20			`* of this software for any purpose.`
21			`*`
22			`* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:`
23			`*`
24			`* COPYRIGHT (c) 1989-1997.`
25			`* On-Line Applications Research Corporation (OAR).`
26			`* Copyright assigned to U.S. Government, 1994.`
27			`*`
28			`* The license and distribution terms for this file may in`
29			`* the file LICENSE in this distribution or at`
30			`* http://www.OARcorp.com/rtems/license.html.`
31			`*`
32			`* $Id: cpu_asm.S,v 1.2 2001-09-27 11:59:29 chris Exp $`
33			`*/`
34
35			`#include`
36
37			`/*`
38			`* Offsets for various Contexts`
39			`*/`
40			`.set GP_1, 0`
41			`.set GP_2, (GP_1 + 4)`
42			`.set GP_13, (GP_2 + 4)`
43			`.set GP_14, (GP_13 + 4)`
44
45			`.set GP_15, (GP_14 + 4)`
46			`.set GP_16, (GP_15 + 4)`
47			`.set GP_17, (GP_16 + 4)`
48			`.set GP_18, (GP_17 + 4)`
49
50			`.set GP_19, (GP_18 + 4)`
51			`.set GP_20, (GP_19 + 4)`
52			`.set GP_21, (GP_20 + 4)`
53			`.set GP_22, (GP_21 + 4)`
54
55			`.set GP_23, (GP_22 + 4)`
56			`.set GP_24, (GP_23 + 4)`
57			`.set GP_25, (GP_24 + 4)`
58			`.set GP_26, (GP_25 + 4)`
59
60			`.set GP_27, (GP_26 + 4)`
61			`.set GP_28, (GP_27 + 4)`
62			`.set GP_29, (GP_28 + 4)`
63			`.set GP_30, (GP_29 + 4)`
64
65			`.set GP_31, (GP_30 + 4)`
66			`.set GP_CR, (GP_31 + 4)`
67			`.set GP_PC, (GP_CR + 4)`
68			`.set GP_MSR, (GP_PC + 4)`
69
70			`#if (PPC_HAS_DOUBLE == 1)`
71			`.set FP_0, 0`
72			`.set FP_1, (FP_0 + 8)`
73			`.set FP_2, (FP_1 + 8)`
74			`.set FP_3, (FP_2 + 8)`
75			`.set FP_4, (FP_3 + 8)`
76			`.set FP_5, (FP_4 + 8)`
77			`.set FP_6, (FP_5 + 8)`
78			`.set FP_7, (FP_6 + 8)`
79			`.set FP_8, (FP_7 + 8)`
80			`.set FP_9, (FP_8 + 8)`
81			`.set FP_10, (FP_9 + 8)`
82			`.set FP_11, (FP_10 + 8)`
83			`.set FP_12, (FP_11 + 8)`
84			`.set FP_13, (FP_12 + 8)`
85			`.set FP_14, (FP_13 + 8)`
86			`.set FP_15, (FP_14 + 8)`
87			`.set FP_16, (FP_15 + 8)`
88			`.set FP_17, (FP_16 + 8)`
89			`.set FP_18, (FP_17 + 8)`
90			`.set FP_19, (FP_18 + 8)`
91			`.set FP_20, (FP_19 + 8)`
92			`.set FP_21, (FP_20 + 8)`
93			`.set FP_22, (FP_21 + 8)`
94			`.set FP_23, (FP_22 + 8)`
95			`.set FP_24, (FP_23 + 8)`
96			`.set FP_25, (FP_24 + 8)`
97			`.set FP_26, (FP_25 + 8)`
98			`.set FP_27, (FP_26 + 8)`
99			`.set FP_28, (FP_27 + 8)`
100			`.set FP_29, (FP_28 + 8)`
101			`.set FP_30, (FP_29 + 8)`
102			`.set FP_31, (FP_30 + 8)`
103			`.set FP_FPSCR, (FP_31 + 8)`
104			`#else`
105			`.set FP_0, 0`
106			`.set FP_1, (FP_0 + 4)`
107			`.set FP_2, (FP_1 + 4)`
108			`.set FP_3, (FP_2 + 4)`
109			`.set FP_4, (FP_3 + 4)`
110			`.set FP_5, (FP_4 + 4)`
111			`.set FP_6, (FP_5 + 4)`
112			`.set FP_7, (FP_6 + 4)`
113			`.set FP_8, (FP_7 + 4)`
114			`.set FP_9, (FP_8 + 4)`
115			`.set FP_10, (FP_9 + 4)`
116			`.set FP_11, (FP_10 + 4)`
117			`.set FP_12, (FP_11 + 4)`
118			`.set FP_13, (FP_12 + 4)`
119			`.set FP_14, (FP_13 + 4)`
120			`.set FP_15, (FP_14 + 4)`
121			`.set FP_16, (FP_15 + 4)`
122			`.set FP_17, (FP_16 + 4)`
123			`.set FP_18, (FP_17 + 4)`
124			`.set FP_19, (FP_18 + 4)`
125			`.set FP_20, (FP_19 + 4)`
126			`.set FP_21, (FP_20 + 4)`
127			`.set FP_22, (FP_21 + 4)`
128			`.set FP_23, (FP_22 + 4)`
129			`.set FP_24, (FP_23 + 4)`
130			`.set FP_25, (FP_24 + 4)`
131			`.set FP_26, (FP_25 + 4)`
132			`.set FP_27, (FP_26 + 4)`
133			`.set FP_28, (FP_27 + 4)`
134			`.set FP_29, (FP_28 + 4)`
135			`.set FP_30, (FP_29 + 4)`
136			`.set FP_31, (FP_30 + 4)`
137			`.set FP_FPSCR, (FP_31 + 4)`
138			`#endif`
139
140			`.set IP_LINK, 0`
141			`#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)`
142			`.set IP_0, (IP_LINK + 56)`
143			`#else`
144			`.set IP_0, (IP_LINK + 8)`
145			`#endif`
146			`.set IP_2, (IP_0 + 4)`
147
148			`.set IP_3, (IP_2 + 4)`
149			`.set IP_4, (IP_3 + 4)`
150			`.set IP_5, (IP_4 + 4)`
151			`.set IP_6, (IP_5 + 4)`
152
153			`.set IP_7, (IP_6 + 4)`
154			`.set IP_8, (IP_7 + 4)`
155			`.set IP_9, (IP_8 + 4)`
156			`.set IP_10, (IP_9 + 4)`
157
158			`.set IP_11, (IP_10 + 4)`
159			`.set IP_12, (IP_11 + 4)`
160			`.set IP_13, (IP_12 + 4)`
161			`.set IP_28, (IP_13 + 4)`
162
163			`.set IP_29, (IP_28 + 4)`
164			`.set IP_30, (IP_29 + 4)`
165			`.set IP_31, (IP_30 + 4)`
166			`.set IP_CR, (IP_31 + 4)`
167
168			`.set IP_CTR, (IP_CR + 4)`
169			`.set IP_XER, (IP_CTR + 4)`
170			`.set IP_LR, (IP_XER + 4)`
171			`.set IP_PC, (IP_LR + 4)`
172
173			`.set IP_MSR, (IP_PC + 4)`
174			`.set IP_END, (IP_MSR + 16)`
175
176			`/* _CPU_IRQ_info offsets */`
177
178			`/* These must be in this order */`
179			`.set Nest_level, 0`
180			`.set Disable_level, 4`
181			`.set Vector_table, 8`
182			`.set Stack, 12`
183			`#if (PPC_ABI == PPC_ABI_POWEROPEN)`
184			`.set Dispatch_r2, 16`
185			`.set Switch_necessary, 20`
186			`#else`
187			`.set Default_r2, 16`
188			`#if (PPC_ABI != PPC_ABI_GCC27)`
189			`.set Default_r13, 20`
190			`.set Switch_necessary, 24`
191			`#else`
192			`.set Switch_necessary, 20`
193			`#endif`
194			`#endif`
195			`.set Signal, Switch_necessary + 4`
196			`.set msr_initial, Signal + 4`
197
198			`BEGIN_CODE`
199			`/*`
200			`* _CPU_Context_save_fp_context`
201			`*`
202			`* This routine is responsible for saving the FP context`
203			`* at *fp_context_ptr. If the point to load the FP context`
204			`* from is changed then the pointer is modified by this routine.`
205			`*`
206			`* Sometimes a macro implementation of this is in cpu.h which dereferences`
207			`* the ** and a similarly named routine in this file is passed something`
208			`* like a (Context_Control_fp *). The general rule on making this decision`
209			`* is to avoid writing assembly language.`
210			`*/`
211
212			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
213			`PUBLIC_PROC (_CPU_Context_save_fp)`
214			`PROC (_CPU_Context_save_fp):`
215			`#if (PPC_HAS_FPU == 1)`
216			`lwz r3, 0(r3)`
217			`#if (PPC_HAS_DOUBLE == 1)`
218			`stfd f0, FP_0(r3)`
219			`stfd f1, FP_1(r3)`
220			`stfd f2, FP_2(r3)`
221			`stfd f3, FP_3(r3)`
222			`stfd f4, FP_4(r3)`
223			`stfd f5, FP_5(r3)`
224			`stfd f6, FP_6(r3)`
225			`stfd f7, FP_7(r3)`
226			`stfd f8, FP_8(r3)`
227			`stfd f9, FP_9(r3)`
228			`stfd f10, FP_10(r3)`
229			`stfd f11, FP_11(r3)`
230			`stfd f12, FP_12(r3)`
231			`stfd f13, FP_13(r3)`
232			`stfd f14, FP_14(r3)`
233			`stfd f15, FP_15(r3)`
234			`stfd f16, FP_16(r3)`
235			`stfd f17, FP_17(r3)`
236			`stfd f18, FP_18(r3)`
237			`stfd f19, FP_19(r3)`
238			`stfd f20, FP_20(r3)`
239			`stfd f21, FP_21(r3)`
240			`stfd f22, FP_22(r3)`
241			`stfd f23, FP_23(r3)`
242			`stfd f24, FP_24(r3)`
243			`stfd f25, FP_25(r3)`
244			`stfd f26, FP_26(r3)`
245			`stfd f27, FP_27(r3)`
246			`stfd f28, FP_28(r3)`
247			`stfd f29, FP_29(r3)`
248			`stfd f30, FP_30(r3)`
249			`stfd f31, FP_31(r3)`
250			`mffs f2`
251			`stfd f2, FP_FPSCR(r3)`
252			`#else`
253			`stfs f0, FP_0(r3)`
254			`stfs f1, FP_1(r3)`
255			`stfs f2, FP_2(r3)`
256			`stfs f3, FP_3(r3)`
257			`stfs f4, FP_4(r3)`
258			`stfs f5, FP_5(r3)`
259			`stfs f6, FP_6(r3)`
260			`stfs f7, FP_7(r3)`
261			`stfs f8, FP_8(r3)`
262			`stfs f9, FP_9(r3)`
263			`stfs f10, FP_10(r3)`
264			`stfs f11, FP_11(r3)`
265			`stfs f12, FP_12(r3)`
266			`stfs f13, FP_13(r3)`
267			`stfs f14, FP_14(r3)`
268			`stfs f15, FP_15(r3)`
269			`stfs f16, FP_16(r3)`
270			`stfs f17, FP_17(r3)`
271			`stfs f18, FP_18(r3)`
272			`stfs f19, FP_19(r3)`
273			`stfs f20, FP_20(r3)`
274			`stfs f21, FP_21(r3)`
275			`stfs f22, FP_22(r3)`
276			`stfs f23, FP_23(r3)`
277			`stfs f24, FP_24(r3)`
278			`stfs f25, FP_25(r3)`
279			`stfs f26, FP_26(r3)`
280			`stfs f27, FP_27(r3)`
281			`stfs f28, FP_28(r3)`
282			`stfs f29, FP_29(r3)`
283			`stfs f30, FP_30(r3)`
284			`stfs f31, FP_31(r3)`
285			`mffs f2`
286			`stfs f2, FP_FPSCR(r3)`
287			`#endif`
288			`#endif`
289			`blr`
290
291			`/*`
292			`* _CPU_Context_restore_fp_context`
293			`*`
294			`* This routine is responsible for restoring the FP context`
295			`* at *fp_context_ptr. If the point to load the FP context`
296			`* from is changed then the pointer is modified by this routine.`
297			`*`
298			`* Sometimes a macro implementation of this is in cpu.h which dereferences`
299			`* the ** and a similarly named routine in this file is passed something`
300			`* like a (Context_Control_fp *). The general rule on making this decision`
301			`* is to avoid writing assembly language.`
302			`*/`
303
304			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
305			`PUBLIC_PROC (_CPU_Context_restore_fp)`
306			`PROC (_CPU_Context_restore_fp):`
307			`#if (PPC_HAS_FPU == 1)`
308			`lwz r3, 0(r3)`
309			`#if (PPC_HAS_DOUBLE == 1)`
310			`lfd f2, FP_FPSCR(r3)`
311			`mtfsf 255, f2`
312			`lfd f0, FP_0(r3)`
313			`lfd f1, FP_1(r3)`
314			`lfd f2, FP_2(r3)`
315			`lfd f3, FP_3(r3)`
316			`lfd f4, FP_4(r3)`
317			`lfd f5, FP_5(r3)`
318			`lfd f6, FP_6(r3)`
319			`lfd f7, FP_7(r3)`
320			`lfd f8, FP_8(r3)`
321			`lfd f9, FP_9(r3)`
322			`lfd f10, FP_10(r3)`
323			`lfd f11, FP_11(r3)`
324			`lfd f12, FP_12(r3)`
325			`lfd f13, FP_13(r3)`
326			`lfd f14, FP_14(r3)`
327			`lfd f15, FP_15(r3)`
328			`lfd f16, FP_16(r3)`
329			`lfd f17, FP_17(r3)`
330			`lfd f18, FP_18(r3)`
331			`lfd f19, FP_19(r3)`
332			`lfd f20, FP_20(r3)`
333			`lfd f21, FP_21(r3)`
334			`lfd f22, FP_22(r3)`
335			`lfd f23, FP_23(r3)`
336			`lfd f24, FP_24(r3)`
337			`lfd f25, FP_25(r3)`
338			`lfd f26, FP_26(r3)`
339			`lfd f27, FP_27(r3)`
340			`lfd f28, FP_28(r3)`
341			`lfd f29, FP_29(r3)`
342			`lfd f30, FP_30(r3)`
343			`lfd f31, FP_31(r3)`
344			`#else`
345			`lfs f2, FP_FPSCR(r3)`
346			`mtfsf 255, f2`
347			`lfs f0, FP_0(r3)`
348			`lfs f1, FP_1(r3)`
349			`lfs f2, FP_2(r3)`
350			`lfs f3, FP_3(r3)`
351			`lfs f4, FP_4(r3)`
352			`lfs f5, FP_5(r3)`
353			`lfs f6, FP_6(r3)`
354			`lfs f7, FP_7(r3)`
355			`lfs f8, FP_8(r3)`
356			`lfs f9, FP_9(r3)`
357			`lfs f10, FP_10(r3)`
358			`lfs f11, FP_11(r3)`
359			`lfs f12, FP_12(r3)`
360			`lfs f13, FP_13(r3)`
361			`lfs f14, FP_14(r3)`
362			`lfs f15, FP_15(r3)`
363			`lfs f16, FP_16(r3)`
364			`lfs f17, FP_17(r3)`
365			`lfs f18, FP_18(r3)`
366			`lfs f19, FP_19(r3)`
367			`lfs f20, FP_20(r3)`
368			`lfs f21, FP_21(r3)`
369			`lfs f22, FP_22(r3)`
370			`lfs f23, FP_23(r3)`
371			`lfs f24, FP_24(r3)`
372			`lfs f25, FP_25(r3)`
373			`lfs f26, FP_26(r3)`
374			`lfs f27, FP_27(r3)`
375			`lfs f28, FP_28(r3)`
376			`lfs f29, FP_29(r3)`
377			`lfs f30, FP_30(r3)`
378			`lfs f31, FP_31(r3)`
379			`#endif`
380			`#endif`
381			`blr`
382
383
384			`/* _CPU_Context_switch`
385			`*`
386			`* This routine performs a normal non-FP context switch.`
387			`*/`
388			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
389			`PUBLIC_PROC (_CPU_Context_switch)`
390			`PROC (_CPU_Context_switch):`
391			`sync`
392			`isync`
393			`#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */`
394			`stw r1, GP_1(r3)`
395			`lwz r1, GP_1(r4)`
396			`stw r2, GP_2(r3)`
397			`lwz r2, GP_2(r4)`
398			`#if (PPC_USE_MULTIPLE == 1)`
399			`stmw r13, GP_13(r3)`
400			`lmw r13, GP_13(r4)`
401			`#else`
402			`stw r13, GP_13(r3)`
403			`lwz r13, GP_13(r4)`
404			`stw r14, GP_14(r3)`
405			`lwz r14, GP_14(r4)`
406			`stw r15, GP_15(r3)`
407			`lwz r15, GP_15(r4)`
408			`stw r16, GP_16(r3)`
409			`lwz r16, GP_16(r4)`
410			`stw r17, GP_17(r3)`
411			`lwz r17, GP_17(r4)`
412			`stw r18, GP_18(r3)`
413			`lwz r18, GP_18(r4)`
414			`stw r19, GP_19(r3)`
415			`lwz r19, GP_19(r4)`
416			`stw r20, GP_20(r3)`
417			`lwz r20, GP_20(r4)`
418			`stw r21, GP_21(r3)`
419			`lwz r21, GP_21(r4)`
420			`stw r22, GP_22(r3)`
421			`lwz r22, GP_22(r4)`
422			`stw r23, GP_23(r3)`
423			`lwz r23, GP_23(r4)`
424			`stw r24, GP_24(r3)`
425			`lwz r24, GP_24(r4)`
426			`stw r25, GP_25(r3)`
427			`lwz r25, GP_25(r4)`
428			`stw r26, GP_26(r3)`
429			`lwz r26, GP_26(r4)`
430			`stw r27, GP_27(r3)`
431			`lwz r27, GP_27(r4)`
432			`stw r28, GP_28(r3)`
433			`lwz r28, GP_28(r4)`
434			`stw r29, GP_29(r3)`
435			`lwz r29, GP_29(r4)`
436			`stw r30, GP_30(r3)`
437			`lwz r30, GP_30(r4)`
438			`stw r31, GP_31(r3)`
439			`lwz r31, GP_31(r4)`
440			`#endif`
441			`mfcr r5`
442			`stw r5, GP_CR(r3)`
443			`lwz r5, GP_CR(r4)`
444			`mflr r6`
445			`mtcrf 255, r5`
446			`stw r6, GP_PC(r3)`
447			`lwz r6, GP_PC(r4)`
448			`mfmsr r7`
449			`mtlr r6`
450			`stw r7, GP_MSR(r3)`
451			`lwz r7, GP_MSR(r4)`
452			`mtmsr r7`
453			`#endif`
454			`#if (PPC_CACHE_ALIGNMENT == 16)`
455			`/* This assumes that all the registers are in the given order */`
456			`li r5, 16`
457			`addi r3,r3,-4`
458			`#if ( PPC_USE_DATA_CACHE )`
459			`dcbz r5, r3`
460			`#endif`
461			`stw r1, GP_1+4(r3)`
462			`stw r2, GP_2+4(r3)`
463			`#if (PPC_USE_MULTIPLE == 1)`
464			`addi r3, r3, GP_14+4`
465			`#if ( PPC_USE_DATA_CACHE )`
466			`dcbz r5, r3`
467			`#endif`
468
469			`addi r3, r3, GP_18-GP_14`
470			`#if ( PPC_USE_DATA_CACHE )`
471			`dcbz r5, r3`
472			`#endif`
473			`addi r3, r3, GP_22-GP_18`
474			`#if ( PPC_USE_DATA_CACHE )`
475			`dcbz r5, r3`
476			`#endif`
477			`addi r3, r3, GP_26-GP_22`
478			`#if ( PPC_USE_DATA_CACHE )`
479			`dcbz r5, r3`
480			`#endif`
481			`stmw r13, GP_13-GP_26(r3)`
482			`#else`
483			`stw r13, GP_13+4(r3)`
484			`stwu r14, GP_14+4(r3)`
485			`#if ( PPC_USE_DATA_CACHE )`
486			`dcbz r5, r3`
487			`#endif`
488			`stw r15, GP_15-GP_14(r3)`
489			`stw r16, GP_16-GP_14(r3)`
490			`stw r17, GP_17-GP_14(r3)`
491			`stwu r18, GP_18-GP_14(r3)`
492			`#if ( PPC_USE_DATA_CACHE )`
493			`dcbz r5, r3`
494			`#endif`
495			`stw r19, GP_19-GP_18(r3)`
496			`stw r20, GP_20-GP_18(r3)`
497			`stw r21, GP_21-GP_18(r3)`
498			`stwu r22, GP_22-GP_18(r3)`
499			`#if ( PPC_USE_DATA_CACHE )`
500			`dcbz r5, r3`
501			`#endif`
502			`stw r23, GP_23-GP_22(r3)`
503			`stw r24, GP_24-GP_22(r3)`
504			`stw r25, GP_25-GP_22(r3)`
505			`stwu r26, GP_26-GP_22(r3)`
506			`#if ( PPC_USE_DATA_CACHE )`
507			`dcbz r5, r3`
508			`#endif`
509			`stw r27, GP_27-GP_26(r3)`
510			`stw r28, GP_28-GP_26(r3)`
511			`stw r29, GP_29-GP_26(r3)`
512			`stw r30, GP_30-GP_26(r3)`
513			`stw r31, GP_31-GP_26(r3)`
514			`#endif`
515			`#if ( PPC_USE_DATA_CACHE )`
516			`dcbt r0, r4`
517			`#endif`
518			`mfcr r6`
519			`stw r6, GP_CR-GP_26(r3)`
520			`mflr r7`
521			`stw r7, GP_PC-GP_26(r3)`
522			`mfmsr r8`
523			`stw r8, GP_MSR-GP_26(r3)`
524
525			`#if ( PPC_USE_DATA_CACHE )`
526			`dcbt r5, r4`
527			`#endif`
528			`lwz r1, GP_1(r4)`
529			`lwz r2, GP_2(r4)`
530			`#if (PPC_USE_MULTIPLE == 1)`
531			`addi r4, r4, GP_15`
532			`#if ( PPC_USE_DATA_CACHE )`
533			`dcbt r5, r4`
534			`#endif`
535			`addi r4, r4, GP_19-GP_15`
536			`#if ( PPC_USE_DATA_CACHE )`
537			`dcbt r5, r4`
538			`#endif`
539			`addi r4, r4, GP_23-GP_19`
540			`#if ( PPC_USE_DATA_CACHE )`
541			`dcbt r5, r4`
542			`#endif`
543			`addi r4, r4, GP_27-GP_23`
544			`#if ( PPC_USE_DATA_CACHE )`
545			`dcbt r5, r4`
546			`#endif`
547			`lmw r13, GP_13-GP_27(r4)`
548			`#else`
549			`lwz r13, GP_13(r4)`
550			`lwz r14, GP_14(r4)`
551			`lwzu r15, GP_15(r4)`
552			`#if ( PPC_USE_DATA_CACHE )`
553			`dcbt r5, r4`
554			`#endif`
555			`lwz r16, GP_16-GP_15(r4)`
556			`lwz r17, GP_17-GP_15(r4)`
557			`lwz r18, GP_18-GP_15(r4)`
558			`lwzu r19, GP_19-GP_15(r4)`
559			`#if ( PPC_USE_DATA_CACHE )`
560			`dcbt r5, r4`
561			`#endif`
562			`lwz r20, GP_20-GP_19(r4)`
563			`lwz r21, GP_21-GP_19(r4)`
564			`lwz r22, GP_22-GP_19(r4)`
565			`lwzu r23, GP_23-GP_19(r4)`
566			`#if ( PPC_USE_DATA_CACHE )`
567			`dcbt r5, r4`
568			`#endif`
569			`lwz r24, GP_24-GP_23(r4)`
570			`lwz r25, GP_25-GP_23(r4)`
571			`lwz r26, GP_26-GP_23(r4)`
572			`lwzu r27, GP_27-GP_23(r4)`
573			`#if ( PPC_USE_DATA_CACHE )`
574			`dcbt r5, r4`
575			`#endif`
576			`lwz r28, GP_28-GP_27(r4)`
577			`lwz r29, GP_29-GP_27(r4)`
578			`lwz r30, GP_30-GP_27(r4)`
579			`lwz r31, GP_31-GP_27(r4)`
580			`#endif`
581			`lwz r6, GP_CR-GP_27(r4)`
582			`lwz r7, GP_PC-GP_27(r4)`
583			`lwz r8, GP_MSR-GP_27(r4)`
584			`mtcrf 255, r6`
585			`mtlr r7`
586			`mtmsr r8`
587			`#endif`
588			`#if (PPC_CACHE_ALIGNMENT == 32)`
589			`/* This assumes that all the registers are in the given order */`
590			`li r5, 32`
591			`addi r3,r3,-4`
592			`#if ( PPC_USE_DATA_CACHE )`
593			`dcbz r5, r3`
594			`#endif`
595			`stw r1, GP_1+4(r3)`
596			`stw r2, GP_2+4(r3)`
597			`#if (PPC_USE_MULTIPLE == 1)`
598			`addi r3, r3, GP_18+4`
599			`#if ( PPC_USE_DATA_CACHE )`
600			`dcbz r5, r3`
601			`#endif`
602			`stmw r13, GP_13-GP_18(r3)`
603			`#else`
604			`stw r13, GP_13+4(r3)`
605			`stw r14, GP_14+4(r3)`
606			`stw r15, GP_15+4(r3)`
607			`stw r16, GP_16+4(r3)`
608			`stw r17, GP_17+4(r3)`
609			`stwu r18, GP_18+4(r3)`
610			`#if ( PPC_USE_DATA_CACHE )`
611			`dcbz r5, r3`
612			`#endif`
613			`stw r19, GP_19-GP_18(r3)`
614			`stw r20, GP_20-GP_18(r3)`
615			`stw r21, GP_21-GP_18(r3)`
616			`stw r22, GP_22-GP_18(r3)`
617			`stw r23, GP_23-GP_18(r3)`
618			`stw r24, GP_24-GP_18(r3)`
619			`stw r25, GP_25-GP_18(r3)`
620			`stw r26, GP_26-GP_18(r3)`
621			`stw r27, GP_27-GP_18(r3)`
622			`stw r28, GP_28-GP_18(r3)`
623			`stw r29, GP_29-GP_18(r3)`
624			`stw r30, GP_30-GP_18(r3)`
625			`stw r31, GP_31-GP_18(r3)`
626			`#endif`
627			`#if ( PPC_USE_DATA_CACHE )`
628			`dcbt r0, r4`
629			`#endif`
630			`mfcr r6`
631			`stw r6, GP_CR-GP_18(r3)`
632			`mflr r7`
633			`stw r7, GP_PC-GP_18(r3)`
634			`mfmsr r8`
635			`stw r8, GP_MSR-GP_18(r3)`
636
637			`#if ( PPC_USE_DATA_CACHE )`
638			`dcbt r5, r4`
639			`#endif`
640			`lwz r1, GP_1(r4)`
641			`lwz r2, GP_2(r4)`
642			`#if (PPC_USE_MULTIPLE == 1)`
643			`addi r4, r4, GP_19`
644			`#if ( PPC_USE_DATA_CACHE )`
645			`dcbt r5, r4`
646			`#endif`
647			`lmw r13, GP_13-GP_19(r4)`
648			`#else`
649			`lwz r13, GP_13(r4)`
650			`lwz r14, GP_14(r4)`
651			`lwz r15, GP_15(r4)`
652			`lwz r16, GP_16(r4)`
653			`lwz r17, GP_17(r4)`
654			`lwz r18, GP_18(r4)`
655			`lwzu r19, GP_19(r4)`
656			`#if ( PPC_USE_DATA_CACHE )`
657			`dcbt r5, r4`
658			`#endif`
659			`lwz r20, GP_20-GP_19(r4)`
660			`lwz r21, GP_21-GP_19(r4)`
661			`lwz r22, GP_22-GP_19(r4)`
662			`lwz r23, GP_23-GP_19(r4)`
663			`lwz r24, GP_24-GP_19(r4)`
664			`lwz r25, GP_25-GP_19(r4)`
665			`lwz r26, GP_26-GP_19(r4)`
666			`lwz r27, GP_27-GP_19(r4)`
667			`lwz r28, GP_28-GP_19(r4)`
668			`lwz r29, GP_29-GP_19(r4)`
669			`lwz r30, GP_30-GP_19(r4)`
670			`lwz r31, GP_31-GP_19(r4)`
671			`#endif`
672			`lwz r6, GP_CR-GP_19(r4)`
673			`lwz r7, GP_PC-GP_19(r4)`
674			`lwz r8, GP_MSR-GP_19(r4)`
675			`mtcrf 255, r6`
676			`mtlr r7`
677			`mtmsr r8`
678			`#endif`
679			`blr`
680
681			`/*`
682			`* _CPU_Context_restore`
683			`*`
684			`* This routine is generallu used only to restart self in an`
685			`* efficient manner. It may simply be a label in _CPU_Context_switch.`
686			`*`
687			`* NOTE: May be unnecessary to reload some registers.`
688			`*/`
689			`/*`
690			`* ACB: Don't worry about cache optimisation here - this is not THAT critical.`
691			`*/`
692			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
693			`PUBLIC_PROC (_CPU_Context_restore)`
694			`PROC (_CPU_Context_restore):`
695			`lwz r5, GP_CR(r3)`
696			`lwz r6, GP_PC(r3)`
697			`lwz r7, GP_MSR(r3)`
698			`mtcrf 255, r5`
699			`mtlr r6`
700			`mtmsr r7`
701			`lwz r1, GP_1(r3)`
702			`lwz r2, GP_2(r3)`
703			`#if (PPC_USE_MULTIPLE == 1)`
704			`lmw r13, GP_13(r3)`
705			`#else`
706			`lwz r13, GP_13(r3)`
707			`lwz r14, GP_14(r3)`
708			`lwz r15, GP_15(r3)`
709			`lwz r16, GP_16(r3)`
710			`lwz r17, GP_17(r3)`
711			`lwz r18, GP_18(r3)`
712			`lwz r19, GP_19(r3)`
713			`lwz r20, GP_20(r3)`
714			`lwz r21, GP_21(r3)`
715			`lwz r22, GP_22(r3)`
716			`lwz r23, GP_23(r3)`
717			`lwz r24, GP_24(r3)`
718			`lwz r25, GP_25(r3)`
719			`lwz r26, GP_26(r3)`
720			`lwz r27, GP_27(r3)`
721			`lwz r28, GP_28(r3)`
722			`lwz r29, GP_29(r3)`
723			`lwz r30, GP_30(r3)`
724			`lwz r31, GP_31(r3)`
725			`#endif`
726
727			`blr`
728
729			`/* Individual interrupt prologues look like this:`
730			`* #if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)`
731			`* #if (PPC_HAS_FPU)`
732			`* stwu r1, -(204 + 188 + IP_END)(r1)`
733			`* #else`
734			`* stwu r1, -(20*4 + IP_END)(r1)`
735			`* #endif`
736			`* #else`
737			`* stwu r1, -(IP_END)(r1)`
738			`* #endif`
739			`* stw r0, IP_0(r1)`
740			`*`
741			`* li r0, vectornum`
742			`* b PROC (_ISR_Handler{,C})`
743			`*/`
744
745			`/* void __ISR_Handler()`
746			`*`
747			`* This routine provides the RTEMS interrupt management.`
748			`* The vector number is in r0. R0 has already been stacked.`
749			`*`
750			`*/`
751			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
752			`PUBLIC_PROC (_ISR_Handler)`
753			`PROC (_ISR_Handler):`
754			`#define LABEL(x) x`
755			`/* XXX ??`
756			`#define MTSAVE(x) mtspr sprg0, x`
757			`#define MFSAVE(x) mfspr x, sprg0`
758			`*/`
759			`#define MTPC(x) mtspr srr0, x`
760			`#define MFPC(x) mfspr x, srr0`
761			`#define MTMSR(x) mtspr srr1, x`
762			`#define MFMSR(x) mfspr x, srr1`
763
764			`#include "irq_stub.S"`
765			`rfi`
766
767			`#if (PPC_HAS_RFCI == 1)`
768			`/* void __ISR_HandlerC()`
769			`*`
770			`* This routine provides the RTEMS interrupt management.`
771			`* For critical interrupts`
772			`*`
773			`*/`
774			`ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)`
775			`PUBLIC_PROC (_ISR_HandlerC)`
776			`PROC (_ISR_HandlerC):`
777			`#undef LABEL`
778			`#undef MTSAVE`
779			`#undef MFSAVE`
780			`#undef MTPC`
781			`#undef MFPC`
782			`#undef MTMSR`
783			`#undef MFMSR`
784			`#define LABEL(x) x##_C`
785			`/* XXX??`
786			`#define MTSAVE(x) mtspr sprg1, x`
787			`#define MFSAVE(x) mfspr x, sprg1`
788			`*/`
789			`#define MTPC(x) mtspr srr2, x`
790			`#define MFPC(x) mfspr x, srr2`
791			`#define MTMSR(x) mtspr srr3, x`
792			`#define MFMSR(x) mfspr x, srr3`
793			`#include "irq_stub.S"`
794			`rfci`
795			`#endif`
796
797			`/* PowerOpen descriptors for indirect function calls.`
798			`*/`
799
800			`#if (PPC_ABI == PPC_ABI_POWEROPEN)`
801			`DESCRIPTOR (_CPU_Context_save_fp)`
802			`DESCRIPTOR (_CPU_Context_restore_fp)`
803			`DESCRIPTOR (_CPU_Context_switch)`
804			`DESCRIPTOR (_CPU_Context_restore)`
805			`DESCRIPTOR (_ISR_Handler)`
806			`#if (PPC_HAS_RFCI == 1)`
807			`DESCRIPTOR (_ISR_HandlerC)`
808			`#endif`
809			`#endif`