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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [old_exception_processing/] [irq_stub.S] - Blame information for rev 173

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/*
 *  This file contains the interrupt handler assembly code for the PowerPC
 *  implementation of RTEMS.  It is #included from cpu_asm.s.
 *
 *  Author:     Andrew Bray 
 *
 *  COPYRIGHT (c) 1995 by i-cubed ltd.
 *
 *  To anyone who acknowledges that this file is provided "AS IS"
 *  without any express or implied warranty:
 *      permission to use, copy, modify, and distribute this file
 *      for any purpose is hereby granted without fee, provided that
 *      the above copyright notice and this notice appears in all
 *      copies, and that the name of i-cubed limited not be used in
 *      advertising or publicity pertaining to distribution of the
 *      software without specific, written prior permission.
 *      i-cubed limited makes no representations about the suitability
 *      of this software for any purpose.
 *
 *  $Id: irq_stub.S,v 1.2 2001-09-27 11:59:29 chris Exp $
 */
 
/*  void __ISR_Handler()
 *
 *  This routine provides the RTEMS interrupt management.
 *  The vector number is in r0. R0 has already been stacked.
 *
 */
        PUBLIC_VAR (_CPU_IRQ_info )
 
        /* Finish off the interrupt frame */
        stw     r2, IP_2(r1)
        stw     r3, IP_3(r1)
        stw     r4, IP_4(r1)
        stw     r5, IP_5(r1)
        stw     r6, IP_6(r1)
        stw     r7, IP_7(r1)
        stw     r8, IP_8(r1)
        stw     r9, IP_9(r1)
        stw     r10, IP_10(r1)
        stw     r11, IP_11(r1)
        stw     r12, IP_12(r1)
        stw     r13, IP_13(r1)
        stmw    r28, IP_28(r1)
        mfcr    r5
        mfctr   r6
        mfxer   r7
        mflr    r8
        MFPC    (r9)
        MFMSR   (r10)
        /* Establish addressing */
#if (PPC_USE_SPRG)
        mfspr   r11, sprg3
#else
        lis     r11,_CPU_IRQ_info@ha
        addi    r11,r11,_CPU_IRQ_info@l
#endif
#if ( PPC_USE_DATA_CACHE )
        dcbt    r0, r11
#endif
        stw     r5, IP_CR(r1)
        stw     r6, IP_CTR(r1)
        stw     r7, IP_XER(r1)
        stw     r8, IP_LR(r1)
        stw     r9, IP_PC(r1)
        stw     r10, IP_MSR(r1)
 
        lwz     r30, Vector_table(r11)
        slwi    r4,r0,2
        lwz     r28, Nest_level(r11)
        add     r4, r4, r30
 
        lwz     r30, 0(r28)
        mr      r3, r0
        lwz     r31, Stack(r11)
  /*
   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
   *    if ( _ISR_Nest_level == 0 )
   *      switch to software interrupt stack
   *  #endif
   */
        /* Switch stacks, here we must prevent ALL interrupts */
#if (PPC_USE_SPRG)
        mfmsr   r5
        mfspr   r6, sprg2
#else
        lwz     r6,msr_initial(r11)
        lis     r5,~PPC_MSR_DISABLE_MASK@ha
        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
        and     r6,r6,r5
        mfmsr   r5
#endif
        mtmsr   r6
        cmpwi   r30, 0
        lwz     r29, Disable_level(r11)
        subf    r31,r1,r31
        bne     LABEL (nested)
        stwux   r1,r1,r31
LABEL (nested):
  /*
   *  _ISR_Nest_level++;
   */
        lwz     r31, 0(r29)
        addi    r30,r30,1
        stw     r30,0(r28)
        /* From here on out, interrupts can be re-enabled. RTEMS
         * convention says not.
         */
        lwz     r4,0(r4)
  /*
   *  _Thread_Dispatch_disable_level++;
   */
        addi    r31,r31,1
        stw     r31, 0(r29)
/* SCE 980217
 *
 * We need address translation ON when we call our ISR routine
 
        mtmsr   r5
 
 */
 
  /*
   *  (*_ISR_Vector_table[ vector ])( vector );
   */
#if (PPC_ABI == PPC_ABI_POWEROPEN)
        lwz     r6,0(r4)
        lwz     r2,4(r4)
        mtlr    r6
        lwz     r11,8(r4)
#endif
#if (PPC_ABI == PPC_ABI_GCC27)
        lwz     r2, Default_r2(r11)
        mtlr    r4
        #lwz    r2, 0(r2)
#endif
#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI)
        mtlr    r4
        lwz     r2, Default_r2(r11)
        lwz     r13, Default_r13(r11)
        #lwz    r2, 0(r2)
        #lwz    r13, 0(r13)
#endif
        mr      r4,r1
        blrl
        /* NOP marker for debuggers */
        or      r6,r6,r6
 
        /*      We must re-disable the interrupts */
#if (PPC_USE_SPRG)
        mfspr   r11, sprg3
        mfspr   r0, sprg2
#else
        lis     r11,_CPU_IRQ_info@ha
        addi    r11,r11,_CPU_IRQ_info@l
        lwz     r0,msr_initial(r11)
        lis     r30,~PPC_MSR_DISABLE_MASK@ha
        ori     r30,r30,~PPC_MSR_DISABLE_MASK@l
        and     r0,r0,r30
#endif
        mtmsr   r0
        lwz     r30, 0(r28)
        lwz     r31, 0(r29)
 
  /*
   *  if (--Thread_Dispatch_disable,--_ISR_Nest_level)
   *    goto easy_exit;
   */
        addi    r30, r30, -1
        cmpwi   r30, 0
        addi    r31, r31, -1
        stw     r30, 0(r28)
        stw     r31, 0(r29)
        bne     LABEL (easy_exit)
        cmpwi   r31, 0
 
        lwz     r30, Switch_necessary(r11)
 
  /*
   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
   *    restore stack
   *  #endif
   */
        lwz     r1,0(r1)
        bne     LABEL (easy_exit)
        lwz     r30, 0(r30)
        lwz     r31, Signal(r11)
 
  /*
   *  if ( _Context_Switch_necessary )
   *    goto switch
   */
        cmpwi   r30, 0
        lwz     r28, 0(r31)
        li      r6,0
        bne     LABEL (switch)
  /*
   *  if ( !_ISR_Signals_to_thread_executing )
   *    goto easy_exit
   *  _ISR_Signals_to_thread_executing = 0;
   */
        cmpwi   r28, 0
        beq     LABEL (easy_exit)
 
  /*
   * switch:
   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
   */
LABEL (switch):
        stw     r6, 0(r31)
        /* Re-enable interrupts */
        lwz     r0, IP_MSR(r1)
#if (PPC_ABI == PPC_ABI_POWEROPEN)
        lwz     r2, Dispatch_r2(r11)
#else
        /* R2 and R13 still hold their values from the last call */
#endif
        mtmsr   r0
        bl      SYM (_Thread_Dispatch)
        /* NOP marker for debuggers */
        or      r6,r6,r6
  /*
   *  prepare to get out of interrupt
   */
        /* Re-disable IRQs */
#if (PPC_USE_SPRG)
        mfspr   r0, sprg2
#else
        lis     r11,_CPU_IRQ_info@ha
        addi    r11,r11,_CPU_IRQ_info@l
        lwz     r0,msr_initial(r11)
        lis     r5,~PPC_MSR_DISABLE_MASK@ha
        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
        and     r0,r0,r5
#endif
        mtmsr   r0
 
  /*
   *  easy_exit:
   *  prepare to get out of interrupt
   *  return from interrupt
   */
LABEL (easy_exit):
        lwz     r5, IP_CR(r1)
        lwz     r6, IP_CTR(r1)
        lwz     r7, IP_XER(r1)
        lwz     r8, IP_LR(r1)
        lwz     r9, IP_PC(r1)
        lwz     r10, IP_MSR(r1)
        mtcrf   255,r5
        mtctr   r6
        mtxer   r7
        mtlr    r8
        MTPC    (r9)
        MTMSR   (r10)
        lwz     r0, IP_0(r1)
        lwz     r2, IP_2(r1)
        lwz     r3, IP_3(r1)
        lwz     r4, IP_4(r1)
        lwz     r5, IP_5(r1)
        lwz     r6, IP_6(r1)
        lwz     r7, IP_7(r1)
        lwz     r8, IP_8(r1)
        lwz     r9, IP_9(r1)
        lwz     r10, IP_10(r1)
        lwz     r11, IP_11(r1)
        lwz     r12, IP_12(r1)
        lwz     r13, IP_13(r1)
        lmw     r28, IP_28(r1)
        lwz     r1, 0(r1)

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [old_exception_processing/] [irq_stub.S] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* This file contains the interrupt handler assembly code for the PowerPC`
3			`* implementation of RTEMS. It is #included from cpu_asm.s.`
4			`*`
5			`* Author: Andrew Bray`
6			`*`
7			`* COPYRIGHT (c) 1995 by i-cubed ltd.`
8			`*`
9			`* To anyone who acknowledges that this file is provided "AS IS"`
10			`* without any express or implied warranty:`
11			`* permission to use, copy, modify, and distribute this file`
12			`* for any purpose is hereby granted without fee, provided that`
13			`* the above copyright notice and this notice appears in all`
14			`* copies, and that the name of i-cubed limited not be used in`
15			`* advertising or publicity pertaining to distribution of the`
16			`* software without specific, written prior permission.`
17			`* i-cubed limited makes no representations about the suitability`
18			`* of this software for any purpose.`
19			`*`
20			`* $Id: irq_stub.S,v 1.2 2001-09-27 11:59:29 chris Exp $`
21			`*/`
22
23			`/* void __ISR_Handler()`
24			`*`
25			`* This routine provides the RTEMS interrupt management.`
26			`* The vector number is in r0. R0 has already been stacked.`
27			`*`
28			`*/`
29			`PUBLIC_VAR (_CPU_IRQ_info )`
30
31			`/* Finish off the interrupt frame */`
32			`stw r2, IP_2(r1)`
33			`stw r3, IP_3(r1)`
34			`stw r4, IP_4(r1)`
35			`stw r5, IP_5(r1)`
36			`stw r6, IP_6(r1)`
37			`stw r7, IP_7(r1)`
38			`stw r8, IP_8(r1)`
39			`stw r9, IP_9(r1)`
40			`stw r10, IP_10(r1)`
41			`stw r11, IP_11(r1)`
42			`stw r12, IP_12(r1)`
43			`stw r13, IP_13(r1)`
44			`stmw r28, IP_28(r1)`
45			`mfcr r5`
46			`mfctr r6`
47			`mfxer r7`
48			`mflr r8`
49			`MFPC (r9)`
50			`MFMSR (r10)`
51			`/* Establish addressing */`
52			`#if (PPC_USE_SPRG)`
53			`mfspr r11, sprg3`
54			`#else`
55			`lis r11,_CPU_IRQ_info@ha`
56			`addi r11,r11,_CPU_IRQ_info@l`
57			`#endif`
58			`#if ( PPC_USE_DATA_CACHE )`
59			`dcbt r0, r11`
60			`#endif`
61			`stw r5, IP_CR(r1)`
62			`stw r6, IP_CTR(r1)`
63			`stw r7, IP_XER(r1)`
64			`stw r8, IP_LR(r1)`
65			`stw r9, IP_PC(r1)`
66			`stw r10, IP_MSR(r1)`
67
68			`lwz r30, Vector_table(r11)`
69			`slwi r4,r0,2`
70			`lwz r28, Nest_level(r11)`
71			`add r4, r4, r30`
72
73			`lwz r30, 0(r28)`
74			`mr r3, r0`
75			`lwz r31, Stack(r11)`
76			`/*`
77			`* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )`
78			`* if ( _ISR_Nest_level == 0 )`
79			`* switch to software interrupt stack`
80			`* #endif`
81			`*/`
82			`/* Switch stacks, here we must prevent ALL interrupts */`
83			`#if (PPC_USE_SPRG)`
84			`mfmsr r5`
85			`mfspr r6, sprg2`
86			`#else`
87			`lwz r6,msr_initial(r11)`
88			`lis r5,~PPC_MSR_DISABLE_MASK@ha`
89			`ori r5,r5,~PPC_MSR_DISABLE_MASK@l`
90			`and r6,r6,r5`
91			`mfmsr r5`
92			`#endif`
93			`mtmsr r6`
94			`cmpwi r30, 0`
95			`lwz r29, Disable_level(r11)`
96			`subf r31,r1,r31`
97			`bne LABEL (nested)`
98			`stwux r1,r1,r31`
99			`LABEL (nested):`
100			`/*`
101			`* _ISR_Nest_level++;`
102			`*/`
103			`lwz r31, 0(r29)`
104			`addi r30,r30,1`
105			`stw r30,0(r28)`
106			`/* From here on out, interrupts can be re-enabled. RTEMS`
107			`* convention says not.`
108			`*/`
109			`lwz r4,0(r4)`
110			`/*`
111			`* _Thread_Dispatch_disable_level++;`
112			`*/`
113			`addi r31,r31,1`
114			`stw r31, 0(r29)`
115			`/* SCE 980217`
116			`*`
117			`* We need address translation ON when we call our ISR routine`
118
119			`mtmsr r5`
120
121			`*/`
122
123			`/*`
124			`* (*_ISR_Vector_table[ vector ])( vector );`
125			`*/`
126			`#if (PPC_ABI == PPC_ABI_POWEROPEN)`
127			`lwz r6,0(r4)`
128			`lwz r2,4(r4)`
129			`mtlr r6`
130			`lwz r11,8(r4)`
131			`#endif`
132			`#if (PPC_ABI == PPC_ABI_GCC27)`
133			`lwz r2, Default_r2(r11)`
134			`mtlr r4`
135			`#lwz r2, 0(r2)`
136			`#endif`
137			`#if (PPC_ABI == PPC_ABI_SVR4 \|\| PPC_ABI == PPC_ABI_EABI)`
138			`mtlr r4`
139			`lwz r2, Default_r2(r11)`
140			`lwz r13, Default_r13(r11)`
141			`#lwz r2, 0(r2)`
142			`#lwz r13, 0(r13)`
143			`#endif`
144			`mr r4,r1`
145			`blrl`
146			`/* NOP marker for debuggers */`
147			`or r6,r6,r6`
148
149			`/* We must re-disable the interrupts */`
150			`#if (PPC_USE_SPRG)`
151			`mfspr r11, sprg3`
152			`mfspr r0, sprg2`
153			`#else`
154			`lis r11,_CPU_IRQ_info@ha`
155			`addi r11,r11,_CPU_IRQ_info@l`
156			`lwz r0,msr_initial(r11)`
157			`lis r30,~PPC_MSR_DISABLE_MASK@ha`
158			`ori r30,r30,~PPC_MSR_DISABLE_MASK@l`
159			`and r0,r0,r30`
160			`#endif`
161			`mtmsr r0`
162			`lwz r30, 0(r28)`
163			`lwz r31, 0(r29)`
164
165			`/*`
166			`* if (--Thread_Dispatch_disable,--_ISR_Nest_level)`
167			`* goto easy_exit;`
168			`*/`
169			`addi r30, r30, -1`
170			`cmpwi r30, 0`
171			`addi r31, r31, -1`
172			`stw r30, 0(r28)`
173			`stw r31, 0(r29)`
174			`bne LABEL (easy_exit)`
175			`cmpwi r31, 0`
176
177			`lwz r30, Switch_necessary(r11)`
178
179			`/*`
180			`* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )`
181			`* restore stack`
182			`* #endif`
183			`*/`
184			`lwz r1,0(r1)`
185			`bne LABEL (easy_exit)`
186			`lwz r30, 0(r30)`
187			`lwz r31, Signal(r11)`
188
189			`/*`
190			`* if ( _Context_Switch_necessary )`
191			`* goto switch`
192			`*/`
193			`cmpwi r30, 0`
194			`lwz r28, 0(r31)`
195			`li r6,0`
196			`bne LABEL (switch)`
197			`/*`
198			`* if ( !_ISR_Signals_to_thread_executing )`
199			`* goto easy_exit`
200			`* _ISR_Signals_to_thread_executing = 0;`
201			`*/`
202			`cmpwi r28, 0`
203			`beq LABEL (easy_exit)`
204
205			`/*`
206			`* switch:`
207			`* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch`
208			`*/`
209			`LABEL (switch):`
210			`stw r6, 0(r31)`
211			`/* Re-enable interrupts */`
212			`lwz r0, IP_MSR(r1)`
213			`#if (PPC_ABI == PPC_ABI_POWEROPEN)`
214			`lwz r2, Dispatch_r2(r11)`
215			`#else`
216			`/* R2 and R13 still hold their values from the last call */`
217			`#endif`
218			`mtmsr r0`
219			`bl SYM (_Thread_Dispatch)`
220			`/* NOP marker for debuggers */`
221			`or r6,r6,r6`
222			`/*`
223			`* prepare to get out of interrupt`
224			`*/`
225			`/* Re-disable IRQs */`
226			`#if (PPC_USE_SPRG)`
227			`mfspr r0, sprg2`
228			`#else`
229			`lis r11,_CPU_IRQ_info@ha`
230			`addi r11,r11,_CPU_IRQ_info@l`
231			`lwz r0,msr_initial(r11)`
232			`lis r5,~PPC_MSR_DISABLE_MASK@ha`
233			`ori r5,r5,~PPC_MSR_DISABLE_MASK@l`
234			`and r0,r0,r5`
235			`#endif`
236			`mtmsr r0`
237
238			`/*`
239			`* easy_exit:`
240			`* prepare to get out of interrupt`
241			`* return from interrupt`
242			`*/`
243			`LABEL (easy_exit):`
244			`lwz r5, IP_CR(r1)`
245			`lwz r6, IP_CTR(r1)`
246			`lwz r7, IP_XER(r1)`
247			`lwz r8, IP_LR(r1)`
248			`lwz r9, IP_PC(r1)`
249			`lwz r10, IP_MSR(r1)`
250			`mtcrf 255,r5`
251			`mtctr r6`
252			`mtxer r7`
253			`mtlr r8`
254			`MTPC (r9)`
255			`MTMSR (r10)`
256			`lwz r0, IP_0(r1)`
257			`lwz r2, IP_2(r1)`
258			`lwz r3, IP_3(r1)`
259			`lwz r4, IP_4(r1)`
260			`lwz r5, IP_5(r1)`
261			`lwz r6, IP_6(r1)`
262			`lwz r7, IP_7(r1)`
263			`lwz r8, IP_8(r1)`
264			`lwz r9, IP_9(r1)`
265			`lwz r10, IP_10(r1)`
266			`lwz r11, IP_11(r1)`
267			`lwz r12, IP_12(r1)`
268			`lwz r13, IP_13(r1)`
269			`lmw r28, IP_28(r1)`
270			`lwz r1, 0(r1)`