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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [old_exception_processing/] [ppccache.c] - Blame information for rev 773

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Line No. Rev Author Line
1 30 unneback
/*
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 *  PowerPC Cache enable routines
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 *
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 *  $Id: ppccache.c,v 1.2 2001-09-27 11:59:29 chris Exp $
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 */
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#include <rtems/system.h>
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#define PPC_Get_HID0( _value ) \
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  do { \
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      _value = 0;        /* to avoid warnings */ \
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      asm volatile( \
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          "mfspr %0, 0x3f0;"     /* get HID0 */ \
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          "isync" \
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          : "=r" (_value) \
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          : "0" (_value) \
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      ); \
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  } while (0)
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#define PPC_Set_HID0( _value ) \
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  do { \
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      asm volatile( \
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          "isync;" \
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          "mtspr 0x3f0, %0;"     /* load HID0 */ \
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          "isync" \
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          : "=r" (_value) \
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          : "0" (_value) \
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      ); \
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  } while (0)
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void powerpc_instruction_cache_enable ()
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{
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  unsigned32 value;
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  /*
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   * Enable the instruction cache
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   */
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  PPC_Get_HID0( value );
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  value |= 0x00008000;       /* Set ICE bit */
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  PPC_Set_HID0( value );
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}
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void powerpc_data_cache_enable ()
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{
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  unsigned32 value;
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  /*
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   * enable data cache
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   */
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  PPC_Get_HID0( value );
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  value |= 0x00004000;        /* set DCE bit */
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  PPC_Set_HID0( value );
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}
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