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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [sh/] [cpu_asm.c] - Blame information for rev 593

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/*
 *  This file contains the basic algorithms for all assembly code used
 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
 *  in assembly language
 *
 *  NOTE:  This port uses a C file with inline assembler instructions
 *
 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
 *           Bernd Becker (becker@faw.uni-ulm.de)
 *
 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 *
 *  COPYRIGHT (c) 1998.
 *  On-Line Applications Research Corporation (OAR).
 *  Copyright assigned to U.S. Government, 1994.
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: cpu_asm.c,v 1.2 2001-09-27 11:59:30 chris Exp $
 *
 *  This material may be reproduced by or for the U.S. Government pursuant
 *  to the copyright license under the clause at DFARS 252.227-7013.  This
 *  notice must appear in all copies of this file and its derivatives.
 *
 */
 
/*
 *  This is supposed to be an assembly file.  This means that system.h
 *  and cpu.h should not be included in a "real" cpu_asm file.  An
 *  implementation in assembly should include "cpu_asm.h"
 */
 
#include <rtems/system.h>
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/thread.h>
#include <rtems/score/sh.h>
 
#if defined(sh7032)
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
#elif defined (sh7045)
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
#endif
 
#include <rtems/score/sh_io.h>
 
/* from cpu_isps.c */
extern proc_ptr         _Hardware_isr_Table[];
 
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
  unsigned long    *_old_stack_ptr;
#endif
 
register unsigned long  *stack_ptr asm("r15");
 
/*
 * sh_set_irq_priority
 *
 * this function sets the interrupt level of the specified interrupt
 *
 * parameters:
 *             - irq : interrupt number
 *             - prio: priority to set for this interrupt number
 *
 * returns:    0 if ok
 *             -1 on error
 */
 
unsigned int sh_set_irq_priority(
  unsigned int irq,
  unsigned int prio )
{
  unsigned32 shiftcount;
  unsigned32 prioreg;
  unsigned16 temp16;
  unsigned32 level;
 
  /*
   * first check for valid interrupt
   */
  if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
    return -1;
  /*
   * check for valid irq priority
   */
  if( prio > 15 )
    return -1;
 
  /*
   * look up appropriate interrupt priority register
   */
  if( irq > 71)
    {
      irq = irq - 72;
      shiftcount = 12 - ((irq & ~0x03) % 16);
 
      switch( irq / 16)
        {
        case 0: { prioreg = INTC_IPRC; break;}
        case 1: { prioreg = INTC_IPRD; break;}
        case 2: { prioreg = INTC_IPRE; break;}
        default: return -1;
        }
    }
  else
    {
      shiftcount = 12 - 4 * ( irq % 4);
      if( irq > 67)
        prioreg = INTC_IPRB;
      else
        prioreg = INTC_IPRA;
    }
 
  /*
   * Set the interrupt priority register
   */
  _CPU_ISR_Disable( level );
 
  temp16 = read16( prioreg);
  temp16 &= ~( 15 << shiftcount);
  temp16 |= prio << shiftcount;
  write16( temp16, prioreg);
 
  _CPU_ISR_Enable( level );
 
  return 0;
}
 
/*
 *  _CPU_Context_save_fp_context
 *
 *  This routine is responsible for saving the FP context
 *  at *fp_context_ptr.  If the point to load the FP context
 *  from is changed then the pointer is modified by this routine.
 *
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
 *  the ** and a similarly named routine in this file is passed something
 *  like a (Context_Control_fp *).  The general rule on making this decision
 *  is to avoid writing assembly language.
 */
 
void _CPU_Context_save_fp(
  void **fp_context_ptr
)
{
}
 
/*
 *  _CPU_Context_restore_fp_context
 *
 *  This routine is responsible for restoring the FP context
 *  at *fp_context_ptr.  If the point to load the FP context
 *  from is changed then the pointer is modified by this routine.
 *
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
 *  the ** and a similarly named routine in this file is passed something
 *  like a (Context_Control_fp *).  The general rule on making this decision
 *  is to avoid writing assembly language.
 */
 
void _CPU_Context_restore_fp(
  void **fp_context_ptr
)
{
}
 
/*  _CPU_Context_switch
 *
 *  This routine performs a normal non-FP context switch.
 */
 
/*  within __CPU_Context_switch:
 *  _CPU_Context_switch
 *  _CPU_Context_restore
 *
 *  This routine is generally used only to restart self in an
 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
 *
 * NOTE: It should be safe not to store r4, r5
 *
 * NOTE: It is doubtful if r0 is really needed to be stored
 *
 * NOTE: gbr is added, but should not be necessary, as it is
 *      only used globally in this port.
 */
 
/*
 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
 *        the offset each time Context_Control is changed
 */
void __CPU_Context_switch(
  Context_Control  *run,        /* r4 */
  Context_Control  *heir        /* r5 */
)
{
 
asm volatile("
        .global __CPU_Context_switch
__CPU_Context_switch:
 
        add     %0,r4
 
        stc.l   sr,@-r4
        stc.l   gbr,@-r4
        mov.l   r0,@-r4
        mov.l   r1,@-r4
        mov.l   r2,@-r4
        mov.l   r3,@-r4
 
        mov.l   r6,@-r4
        mov.l   r7,@-r4
        mov.l   r8,@-r4
        mov.l   r9,@-r4
        mov.l   r10,@-r4
        mov.l   r11,@-r4
        mov.l   r12,@-r4
        mov.l   r13,@-r4
        mov.l   r14,@-r4
        sts.l   pr,@-r4
        sts.l   mach,@-r4
        sts.l   macl,@-r4
        mov.l   r15,@-r4
 
        mov     r5, r4"
  :: "I" (sizeof(Context_Control))
  );
 
  asm volatile("
        .global __CPU_Context_restore
__CPU_Context_restore:
        mov.l   @r4+,r15
        lds.l   @r4+,macl
        lds.l   @r4+,mach
        lds.l   @r4+,pr
        mov.l   @r4+,r14
        mov.l   @r4+,r13
        mov.l   @r4+,r12
        mov.l   @r4+,r11
        mov.l   @r4+,r10
        mov.l   @r4+,r9
        mov.l   @r4+,r8
        mov.l   @r4+,r7
        mov.l   @r4+,r6
 
        mov.l   @r4+,r3
        mov.l   @r4+,r2
        mov.l   @r4+,r1
        mov.l   @r4+,r0
        ldc.l   @r4+,gbr
        ldc.l   @r4+,sr
 
        rts
        nop" );
}
 
/*
 *  This routine provides the RTEMS interrupt management.
 */
 
void __ISR_Handler( unsigned32 vector)
{
  register unsigned32 level;
 
  _CPU_ISR_Disable( level );
 
  _Thread_Dispatch_disable_level++;
 
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
  if( _ISR_Nest_level == 0 )
    {
      /* Install irq stack */
      _old_stack_ptr = stack_ptr;
      stack_ptr = _CPU_Interrupt_stack_high;
    }
 
#endif
 
  _ISR_Nest_level++;
 
  _CPU_ISR_Enable( level );
 
  /* call isp */
  if( _ISR_Vector_table[ vector])
    (*_ISR_Vector_table[ vector ])( vector );
 
  _CPU_ISR_Disable( level );
 
  _ISR_Nest_level--;
 
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
 
  if( _ISR_Nest_level == 0 )
    /* restore old stack pointer */
    stack_ptr = _old_stack_ptr;
#endif
 
  _Thread_Dispatch_disable_level--;
 
  _CPU_ISR_Enable( level );
 
  if ( _Thread_Dispatch_disable_level == 0 )
    {
      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
        {
          _ISR_Signals_to_thread_executing = FALSE;
          _Thread_Dispatch();
        }
  }
}

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [sh/] [cpu_asm.c] - Blame information for rev 593

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* This file contains the basic algorithms for all assembly code used`
3			`* in an specific CPU port of RTEMS. These algorithms must be implemented`
4			`* in assembly language`
5			`*`
6			`* NOTE: This port uses a C file with inline assembler instructions`
7			`*`
8			`* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and`
9			`* Bernd Becker (becker@faw.uni-ulm.de)`
10			`*`
11			`* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany`
12			`*`
13			`* This program is distributed in the hope that it will be useful,`
14			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.`
16			`*`
17			`*`
18			`* COPYRIGHT (c) 1998.`
19			`* On-Line Applications Research Corporation (OAR).`
20			`* Copyright assigned to U.S. Government, 1994.`
21			`*`
22			`* The license and distribution terms for this file may be`
23			`* found in the file LICENSE in this distribution or at`
24			`* http://www.OARcorp.com/rtems/license.html.`
25			`*`
26			`* $Id: cpu_asm.c,v 1.2 2001-09-27 11:59:30 chris Exp $`
27			`*`
28			`* This material may be reproduced by or for the U.S. Government pursuant`
29			`* to the copyright license under the clause at DFARS 252.227-7013. This`
30			`* notice must appear in all copies of this file and its derivatives.`
31			`*`
32			`*/`
33
34			`/*`
35			`* This is supposed to be an assembly file. This means that system.h`
36			`* and cpu.h should not be included in a "real" cpu_asm file. An`
37			`* implementation in assembly should include "cpu_asm.h"`
38			`*/`
39
40			`#include <rtems/system.h>`
41			`#include <rtems/score/cpu.h>`
42			`#include <rtems/score/isr.h>`
43			`#include <rtems/score/thread.h>`
44			`#include <rtems/score/sh.h>`
45
46			`#if defined(sh7032)`
47			`#include <rtems/score/ispsh7032.h>`
48			`#include <rtems/score/iosh7032.h>`
49			`#elif defined (sh7045)`
50			`#include <rtems/score/ispsh7045.h>`
51			`#include <rtems/score/iosh7045.h>`
52			`#endif`
53
54			`#include <rtems/score/sh_io.h>`
55
56			`/* from cpu_isps.c */`
57			`extern proc_ptr _Hardware_isr_Table[];`
58
59			`#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)`
60			`unsigned long *_old_stack_ptr;`
61			`#endif`
62
63			`register unsigned long *stack_ptr asm("r15");`
64
65			`/*`
66			`* sh_set_irq_priority`
67			`*`
68			`* this function sets the interrupt level of the specified interrupt`
69			`*`
70			`* parameters:`
71			`* - irq : interrupt number`
72			`* - prio: priority to set for this interrupt number`
73			`*`
74			`* returns: 0 if ok`
75			`* -1 on error`
76			`*/`
77
78			`unsigned int sh_set_irq_priority(`
79			`unsigned int irq,`
80			`unsigned int prio )`
81			`{`
82			`unsigned32 shiftcount;`
83			`unsigned32 prioreg;`
84			`unsigned16 temp16;`
85			`unsigned32 level;`
86
87			`/*`
88			`* first check for valid interrupt`
89			`*/`
90			`if(( irq > 113) \|\| (_Hardware_isr_Table[irq] == _dummy_isp))`
91			`return -1;`
92			`/*`
93			`* check for valid irq priority`
94			`*/`
95			`if( prio > 15 )`
96			`return -1;`
97
98			`/*`
99			`* look up appropriate interrupt priority register`
100			`*/`
101			`if( irq > 71)`
102			`{`
103			`irq = irq - 72;`
104			`shiftcount = 12 - ((irq & ~0x03) % 16);`
105
106			`switch( irq / 16)`
107			`{`
108			`case 0: { prioreg = INTC_IPRC; break;}`
109			`case 1: { prioreg = INTC_IPRD; break;}`
110			`case 2: { prioreg = INTC_IPRE; break;}`
111			`default: return -1;`
112			`}`
113			`}`
114			`else`
115			`{`
116			`shiftcount = 12 - 4 * ( irq % 4);`
117			`if( irq > 67)`
118			`prioreg = INTC_IPRB;`
119			`else`
120			`prioreg = INTC_IPRA;`
121			`}`
122
123			`/*`
124			`* Set the interrupt priority register`
125			`*/`
126			`_CPU_ISR_Disable( level );`
127
128			`temp16 = read16( prioreg);`
129			`temp16 &= ~( 15 << shiftcount);`
130			`temp16 \|= prio << shiftcount;`
131			`write16( temp16, prioreg);`
132
133			`_CPU_ISR_Enable( level );`
134
135			`return 0;`
136			`}`
137
138			`/*`
139			`* _CPU_Context_save_fp_context`
140			`*`
141			`* This routine is responsible for saving the FP context`
142			`* at *fp_context_ptr. If the point to load the FP context`
143			`* from is changed then the pointer is modified by this routine.`
144			`*`
145			`* Sometimes a macro implementation of this is in cpu.h which dereferences`
146			`* the ** and a similarly named routine in this file is passed something`
147			`* like a (Context_Control_fp *). The general rule on making this decision`
148			`* is to avoid writing assembly language.`
149			`*/`
150
151			`void _CPU_Context_save_fp(`
152			`void **fp_context_ptr`
153			`)`
154			`{`
155			`}`
156
157			`/*`
158			`* _CPU_Context_restore_fp_context`
159			`*`
160			`* This routine is responsible for restoring the FP context`
161			`* at *fp_context_ptr. If the point to load the FP context`
162			`* from is changed then the pointer is modified by this routine.`
163			`*`
164			`* Sometimes a macro implementation of this is in cpu.h which dereferences`
165			`* the ** and a similarly named routine in this file is passed something`
166			`* like a (Context_Control_fp *). The general rule on making this decision`
167			`* is to avoid writing assembly language.`
168			`*/`
169
170			`void _CPU_Context_restore_fp(`
171			`void **fp_context_ptr`
172			`)`
173			`{`
174			`}`
175
176			`/* _CPU_Context_switch`
177			`*`
178			`* This routine performs a normal non-FP context switch.`
179			`*/`
180
181			`/* within __CPU_Context_switch:`
182			`* _CPU_Context_switch`
183			`* _CPU_Context_restore`
184			`*`
185			`* This routine is generally used only to restart self in an`
186			`* efficient manner. It may simply be a label in _CPU_Context_switch.`
187			`*`
188			`* NOTE: It should be safe not to store r4, r5`
189			`*`
190			`* NOTE: It is doubtful if r0 is really needed to be stored`
191			`*`
192			`* NOTE: gbr is added, but should not be necessary, as it is`
193			`* only used globally in this port.`
194			`*/`
195
196			`/*`
197			`* FIXME: This is an ugly hack, but we wanted to avoid recalculating`
198			`* the offset each time Context_Control is changed`
199			`*/`
200			`void __CPU_Context_switch(`
201			`Context_Control run, / r4 */`
202			`Context_Control heir / r5 */`
203			`)`
204			`{`
205
206			`asm volatile("`
207			`.global __CPU_Context_switch`
208			`__CPU_Context_switch:`
209
210			`add %0,r4`
211
212			`stc.l sr,@-r4`
213			`stc.l gbr,@-r4`
214			`mov.l r0,@-r4`
215			`mov.l r1,@-r4`
216			`mov.l r2,@-r4`
217			`mov.l r3,@-r4`
218
219			`mov.l r6,@-r4`
220			`mov.l r7,@-r4`
221			`mov.l r8,@-r4`
222			`mov.l r9,@-r4`
223			`mov.l r10,@-r4`
224			`mov.l r11,@-r4`
225			`mov.l r12,@-r4`
226			`mov.l r13,@-r4`
227			`mov.l r14,@-r4`
228			`sts.l pr,@-r4`
229			`sts.l mach,@-r4`
230			`sts.l macl,@-r4`
231			`mov.l r15,@-r4`
232
233			`mov r5, r4"`
234			`:: "I" (sizeof(Context_Control))`
235			`);`
236
237			`asm volatile("`
238			`.global __CPU_Context_restore`
239			`__CPU_Context_restore:`
240			`mov.l @r4+,r15`
241			`lds.l @r4+,macl`
242			`lds.l @r4+,mach`
243			`lds.l @r4+,pr`
244			`mov.l @r4+,r14`
245			`mov.l @r4+,r13`
246			`mov.l @r4+,r12`
247			`mov.l @r4+,r11`
248			`mov.l @r4+,r10`
249			`mov.l @r4+,r9`
250			`mov.l @r4+,r8`
251			`mov.l @r4+,r7`
252			`mov.l @r4+,r6`
253
254			`mov.l @r4+,r3`
255			`mov.l @r4+,r2`
256			`mov.l @r4+,r1`
257			`mov.l @r4+,r0`
258			`ldc.l @r4+,gbr`
259			`ldc.l @r4+,sr`
260
261			`rts`
262			`nop" );`
263			`}`
264
265			`/*`
266			`* This routine provides the RTEMS interrupt management.`
267			`*/`
268
269			`void __ISR_Handler( unsigned32 vector)`
270			`{`
271			`register unsigned32 level;`
272
273			`_CPU_ISR_Disable( level );`
274
275			`_Thread_Dispatch_disable_level++;`
276
277			`#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)`
278			`if( _ISR_Nest_level == 0 )`
279			`{`
280			`/* Install irq stack */`
281			`_old_stack_ptr = stack_ptr;`
282			`stack_ptr = _CPU_Interrupt_stack_high;`
283			`}`
284
285			`#endif`
286
287			`_ISR_Nest_level++;`
288
289			`_CPU_ISR_Enable( level );`
290
291			`/* call isp */`
292			`if( _ISR_Vector_table[ vector])`
293			`(*_ISR_Vector_table[ vector ])( vector );`
294
295			`_CPU_ISR_Disable( level );`
296
297			`_ISR_Nest_level--;`
298
299			`#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)`
300
301			`if( _ISR_Nest_level == 0 )`
302			`/* restore old stack pointer */`
303			`stack_ptr = _old_stack_ptr;`
304			`#endif`
305
306			`_Thread_Dispatch_disable_level--;`
307
308			`_CPU_ISR_Enable( level );`
309
310			`if ( _Thread_Dispatch_disable_level == 0 )`
311			`{`
312			`if(( _Context_Switch_necessary) \|\| (! _ISR_Signals_to_thread_executing))`
313			`{`
314			`_ISR_Signals_to_thread_executing = FALSE;`
315			`_Thread_Dispatch();`
316			`}`
317			`}`
318			`}`