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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [sh/] [ispsh7032.c] - Blame information for rev 590

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1 30 unneback 
/*
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 * This file contains the isp frames for the user interrupts.
3 
 * From these procedures __ISR_Handler is called with the vector number
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 * as argument.
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 *
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 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
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 * some releases of gcc doesn't properly handle #pragma interrupt, if a
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 * file contains both isrs and normal functions.
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 *
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 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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 *           Bernd Becker (becker@faw.uni-ulm.de)
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 *
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 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
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 *
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 *
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 *  COPYRIGHT (c) 1998.
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 *  On-Line Applications Research Corporation (OAR).
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 *  Copyright assigned to U.S. Government, 1994.
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: ispsh7032.c,v 1.2 2001-09-27 11:59:30 chris Exp $
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 */
30 
 
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#include <rtems/system.h>
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#include <rtems/score/shtypes.h>
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#include <rtems/score/ispsh7032.h>
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35 
#if !defined(sh7032)
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#error Wrong CPU MODEL
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#endif
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/*
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 * This is an exception vector table
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 *
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 * It has the same structure like the actual vector table (vectab)
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 */
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proc_ptr _Hardware_isr_Table[256]={
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp,
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_nmi_isp, _usb_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp,
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/* trapa 0 -31 */
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
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/* irq 64 ... */
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_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
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_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
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_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
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_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
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_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
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_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
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_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
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_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
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_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
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_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
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_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
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_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
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_wdt_isp,
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/* 113 */ _dref_isp
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};
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80 
#define Str(a)#a
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82 
/*
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 * Some versions of gcc and all version of egcs at least until egcs-1.1b
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 * are not able to handle #pragma interrupt correctly if more than 1 isr is
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 * contained in a file and when optimizing.
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 * We try to work around this problem by using the macro below.
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 */
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#define isp( name, number, func)\
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asm (".global _"Str(name)"\n\t" \
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     "_"Str(name)":       \n\t" \
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     "    mov.l r0,@-r15   \n\t" \
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     "    mov.l r1,@-r15   \n\t" \
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     "    mov.l r2,@-r15   \n\t" \
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     "    mov.l r3,@-r15   \n\t" \
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     "    mov.l r4,@-r15   \n\t" \
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     "    mov.l r5,@-r15   \n\t" \
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     "    mov.l r6,@-r15   \n\t" \
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     "    mov.l r7,@-r15   \n\t" \
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     "    mov.l r14,@-r15  \n\t" \
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     "    sts.l pr,@-r15   \n\t" \
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     "    sts.l mach,@-r15 \n\t" \
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     "    sts.l macl,@-r15 \n\t" \
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     "    mov r15,r14      \n\t" \
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     "    mov.l "Str(name)"_k, r1\n\t" \
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     "    jsr @r1           \n\t" \
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     "    mov #"Str(number)", r4\n\t" \
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     "    mov   r14,r15    \n\t" \
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     "    lds.l @r15+,macl \n\t" \
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     "    lds.l @r15+,mach \n\t" \
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     "    lds.l @r15+,pr   \n\t" \
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     "    mov.l @r15+,r14  \n\t" \
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     "    mov.l @r15+,r7   \n\t" \
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     "    mov.l @r15+,r6   \n\t" \
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     "    mov.l @r15+,r5   \n\t" \
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     "    mov.l @r15+,r4   \n\t" \
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     "    mov.l @r15+,r3   \n\t" \
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     "    mov.l @r15+,r2   \n\t" \
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     "    mov.l @r15+,r1   \n\t" \
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     "    mov.l @r15+,r0   \n\t" \
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     "    rte              \n\t" \
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     "    nop              \n\t" \
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     "    .align 2         \n\t" \
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     #name"_k: \n\t" \
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     ".long "Str(func));
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126 
/************************************************
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 * Dummy interrupt service procedure for
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 * interrupts being not allowed --> Trap 34
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 ************************************************/
130 
asm(" .section .text
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.global __dummy_isp
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__dummy_isp:
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      mov.l r14,@-r15
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      mov   r15, r14
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      trapa #34
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      mov.l @r15+,r14
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      rte
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      nop");
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/*****************************
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 * Non maskable interrupt
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 *****************************/
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isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
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/*****************************
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 * User break controller
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 *****************************/
148 
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
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150 
/*****************************
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 *  External interrupts 0-7
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 *****************************/
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isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
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isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
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isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
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isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
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isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
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isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
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isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
160 
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
161 
 
162 
/*****************************
163 
 * DMA - controller
164 
 *****************************/
165 
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
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isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
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isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
168 
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
169 
 
170 
 
171 
/*****************************
172 
 * Interrupt timer unit
173 
 *****************************/
174 
 
175 
/*****************************
176 
 * Timer 0
177 
 *****************************/
178 
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
179 
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
180 
isp( _ovi0_isp,  OVI0_ISP_V, ___ISR_Handler);
181 
 
182 
/*****************************
183 
 * Timer 1
184 
 *****************************/
185 
isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
186 
isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
187 
isp( _ovi1_isp,  OVI1_ISP_V, ___ISR_Handler);
188 
 
189 
/*****************************
190 
 * Timer 2
191 
 *****************************/
192 
isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
193 
isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
194 
isp( _ovi2_isp,  OVI2_ISP_V, ___ISR_Handler);
195 
 
196 
/*****************************
197 
 * Timer 3
198 
 *****************************/
199 
isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
200 
isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
201 
isp( _ovi3_isp,  OVI3_ISP_V, ___ISR_Handler);
202 
 
203 
/*****************************
204 
 * Timer 4
205 
 *****************************/
206 
isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
207 
isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
208 
isp( _ovi4_isp,  OVI4_ISP_V, ___ISR_Handler);
209 
 
210 
 
211 
/*****************************
212 
 * Serial interfaces
213 
 *****************************/
214 
 
215 
/*****************************
216 
 * Serial interface 0
217 
 *****************************/
218 
isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
219 
isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
220 
isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
221 
isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
222 
 
223 
/*****************************
224 
 * Serial interface 1
225 
 *****************************/
226 
isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
227 
isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
228 
isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
229 
isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
230 
 
231 
 
232 
/*****************************
233 
 * Parity control unit of
234 
 * the bus state controller
235 
 *****************************/
236 
isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler);
237 
 
238 
 
239 
/******************************
240 
 * Analog digital converter
241 
 * ADC
242 
 ******************************/
243 
isp( _adu_isp,  ADU_ISP_V, ___ISR_Handler);
244 
 
245 
 
246 
/******************************
247 
 *  Watchdog timer
248 
 ******************************/
249 
isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
250 
 
251 
 
252 
/******************************
253 
 * DRAM refresh control unit
254 
 * of bus state controller
255 
 ******************************/
256 
isp( _dref_isp,  DREF_ISP_V, ___ISR_Handler);

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