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/*
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* This include file contains information pertaining to the Hitachi SH
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* processor.
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*
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* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
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*
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* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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* Bernd Becker (becker@faw.uni-ulm.de)
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*
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* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
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* contained no copyright notice.
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*
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* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* COPYRIGHT (c) 1998.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: iosh7032.h,v 1.2 2001-09-27 11:59:30 chris Exp $
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*/
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#ifndef __IOSH7030_H
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#define __IOSH7030_H
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/*
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* After each line is explained whether the access is char short or long.
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* The functions read/writeb, w, l, 8, 16, 32 can be found
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* in exec/score/cpu/sh/sh_io.h
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*
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* 8 bit == char ( readb, writeb, read8, write8)
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* 16 bit == short ( readw, writew, read16, write16 )
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* 32 bit == long ( readl, writel, read32, write32 )
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*/
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#define SCI0_SMR 0x05fffec0 /* char */
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#define SCI0_BRR 0x05fffec1 /* char */
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#define SCI0_SCR 0x05fffec2 /* char */
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#define SCI0_TDR 0x05fffec3 /* char */
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#define SCI0_SSR 0x05fffec4 /* char */
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#define SCI0_RDR 0x05fffec5 /* char */
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#define SCI1_SMR 0x05fffec8 /* char */
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#define SCI1_BRR 0x05fffec9 /* char */
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#define SCI1_SCR 0x05fffeca /* char */
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#define SCI1_TDR 0x05fffecb /* char */
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#define SCI1_SSR 0x05fffecc /* char */
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#define SCI1_RDR 0x05fffecd /* char */
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#define ADDRAH 0x05fffee0 /* char */
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#define ADDRAL 0x05fffee1 /* char */
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#define ADDRBH 0x05fffee2 /* char */
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#define ADDRBL 0x05fffee3 /* char */
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#define ADDRCH 0x05fffee4 /* char */
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#define ADDRCL 0x05fffee5 /* char */
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#define ADDRDH 0x05fffee6 /* char */
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#define ADDRDL 0x05fffee7 /* char */
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#define AD_DRA 0x05fffee0 /* short */
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#define AD_DRB 0x05fffee2 /* short */
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#define AD_DRC 0x05fffee4 /* short */
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#define AD_DRD 0x05fffee6 /* short */
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#define ADCSR 0x05fffee8 /* char */
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#define ADCR 0x05fffee9 /* char */
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/*ITU SHARED*/
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#define ITU_TSTR 0x05ffff00 /* char */
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#define ITU_TSNC 0x05ffff01 /* char */
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#define ITU_TMDR 0x05ffff02 /* char */
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#define ITU_TFCR 0x05ffff03 /* char */
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/*ITU CHANNEL 0*/
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#define ITU_TCR0 0x05ffff04 /* char */
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#define ITU_TIOR0 0x05ffff05 /* char */
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#define ITU_TIER0 0x05ffff06 /* char */
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#define ITU_TSR0 0x05ffff07 /* char */
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#define ITU_TCNT0 0x05ffff08 /* short */
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#define ITU_GRA0 0x05ffff0a /* short */
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#define ITU_GRB0 0x05ffff0c /* short */
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/*ITU CHANNEL 1*/
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#define ITU_TCR1 0x05ffff0E /* char */
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#define ITU_TIOR1 0x05ffff0F /* char */
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#define ITU_TIER1 0x05ffff10 /* char */
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#define ITU_TSR1 0x05ffff11 /* char */
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#define ITU_TCNT1 0x05ffff12 /* short */
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#define ITU_GRA1 0x05ffff14 /* short */
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#define ITU_GRB1 0x05ffff16 /* short */
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/*ITU CHANNEL 2*/
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#define ITU_TCR2 0x05ffff18 /* char */
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#define ITU_TIOR2 0x05ffff19 /* char */
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#define ITU_TIER2 0x05ffff1A /* char */
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#define ITU_TSR2 0x05ffff1B /* char */
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#define ITU_TCNT2 0x05ffff1C /* short */
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#define ITU_GRA2 0x05ffff1E /* short */
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#define ITU_GRB2 0x05ffff20 /* short */
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/*ITU CHANNEL 3*/
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#define ITU_TCR3 0x05ffff22 /* char */
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#define ITU_TIOR3 0x05ffff23 /* char */
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#define ITU_TIER3 0x05ffff24 /* char */
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#define ITU_TSR3 0x05ffff25 /* char */
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#define ITU_TCNT3 0x05ffff26 /* short */
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#define ITU_GRA3 0x05ffff28 /* short */
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#define ITU_GRB3 0x05ffff2A /* short */
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#define ITU_BRA3 0x05ffff2C /* short */
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#define ITU_BRB3 0x05ffff2E /* short */
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/*ITU CHANNELS 0-4 SHARED*/
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#define ITU_TOCR 0x05ffff31 /* char */
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/*ITU CHANNEL 4*/
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#define ITU_TCR4 0x05ffff32 /* char */
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#define ITU_TIOR4 0x05ffff33 /* char */
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#define ITU_TIER4 0x05ffff34 /* char */
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#define ITU_TSR4 0x05ffff35 /* char */
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#define ITU_TCNT4 0x05ffff36 /* short */
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#define ITU_GRA4 0x05ffff38 /* short */
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#define ITU_GRB4 0x05ffff3A /* short */
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#define ITU_BRA4 0x05ffff3C /* short */
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#define ITU_BRB4 0x05ffff3E /* short */
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/*DMAC CHANNELS 0-3 SHARED*/
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#define DMAOR 0x05ffff48 /* short */
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/*DMAC CHANNEL 0*/
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#define DMA_SAR0 0x05ffff40 /* long */
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#define DMA_DAR0 0x05ffff44 /* long */
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#define DMA_TCR0 0x05ffff4a /* short */
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#define DMA_CHCR0 0x05ffff4e /* short */
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/*DMAC CHANNEL 1*/
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#define DMA_SAR1 0x05ffff50 /* long */
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#define DMA_DAR1 0x05ffff54 /* long */
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#define DMA_TCR1 0x05fffF5a /* short */
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#define DMA_CHCR1 0x05ffff5e /* short */
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/*DMAC CHANNEL 3*/
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#define DMA_SAR3 0x05ffff60 /* long */
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#define DMA_DAR3 0x05ffff64 /* long */
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#define DMA_TCR3 0x05fffF6a /* short */
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#define DMA_CHCR3 0x05ffff6e /* short */
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/*DMAC CHANNEL 4*/
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#define DMA_SAR4 0x05ffff70 /* long */
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#define DMA_DAR4 0x05ffff74 /* long */
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#define DMA_TCR4 0x05fffF7a /* short */
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#define DMA_CHCR4 0x05ffff7e /* short */
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/*INTC*/
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#define INTC_IPRA 0x05ffff84 /* short */
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#define INTC_IPRB 0x05ffff86 /* short */
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#define INTC_IPRC 0x05ffff88 /* short */
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#define INTC_IPRD 0x05ffff8A /* short */
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#define INTC_IPRE 0x05ffff8C /* short */
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#define INTC_ICR 0x05ffff8E /* short */
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/*UBC*/
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#define UBC_BARH 0x05ffff90 /* short */
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#define UBC_BARL 0x05ffff92 /* short */
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#define UBC_BAMRH 0x05ffff94 /* short */
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#define UBC_BAMRL 0x05ffff96 /* short */
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#define UBC_BBR 0x05ffff98 /* short */
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/*BSC*/
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#define BSC_BCR 0x05ffffA0 /* short */
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#define BSC_WCR1 0x05ffffA2 /* short */
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#define BSC_WCR2 0x05ffffA4 /* short */
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#define BSC_WCR3 0x05ffffA6 /* short */
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#define BSC_DCR 0x05ffffA8 /* short */
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#define BSC_PCR 0x05ffffAA /* short */
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#define BSC_RCR 0x05ffffAC /* short */
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#define BSC_RTCSR 0x05ffffAE /* short */
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#define BSC_RTCNT 0x05ffffB0 /* short */
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#define BSC_RTCOR 0x05ffffB2 /* short */
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/*WDT*/
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#define WDT_TCSR 0x05ffffB8 /* char */
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#define WDT_TCNT 0x05ffffB9 /* char */
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#define WDT_RSTCSR 0x05ffffBB /* char */
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/*POWER DOWN STATE*/
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#define PDT_SBYCR 0x05ffffBC /* char */
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/*PORT A*/
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#define PADR 0x05ffffC0 /* short */
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/*PORT B*/
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#define PBDR 0x05ffffC2 /* short */
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/*PORT C*/
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#define PCDR 0x05ffffD0 /* short */
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/*PFC*/
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#define PFC_PAIOR 0x05ffffC4 /* short */
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#define PFC_PBIOR 0x05ffffC6 /* short */
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#define PFC_PACR1 0x05ffffC8 /* short */
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#define PFC_PACR2 0x05ffffCA /* short */
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#define PFC_PBCR1 0x05ffffCC /* short */
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#define PFC_PBCR2 0x05ffffCE /* short */
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#define PFC_CASCR 0x05ffffEE /* short */
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/*TPC*/
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#define TPC_TPMR 0x05ffffF0 /* short */
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#define TPC_TPCR 0x05ffffF1 /* short */
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#define TPC_NDERH 0x05ffffF2 /* short */
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#define TPC_NDERL 0x05ffffF3 /* short */
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#define TPC_NDRB 0x05ffffF4 /* char */
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#define TPC_NDRA 0x05ffffF5 /* char */
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#define TPC_NDRB1 0x05ffffF6 /* char */
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#define TPC_NDRA1 0x05ffffF7 /* char */
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#endif
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