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/*
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* This include file contains information pertaining to the Hitachi SH
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* processor.
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*
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* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
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*
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* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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* Bernd Becker (becker@faw.uni-ulm.de)
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*
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* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
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* contained no copyright notice.
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*
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* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* COPYRIGHT (c) 1998.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Modified to reflect on-chip registers for sh7045 processor, based on
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* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
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* contained no copyright notice:
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* John M. Mills (jmills@tga.com)
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* TGA Technologies, Inc.
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* 100 Pinnacle Way, Suite 140
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* Norcross, GA 30071 U.S.A.
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* August, 1999
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*
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* This modified file may be copied and distributed in accordance
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* the above-referenced license. It is provided for critique and
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* developmental purposes without any warranty nor representation
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* by the authors or by TGA Technologies.
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*
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* $Id: iosh7045.h,v 1.2 2001-09-27 11:59:30 chris Exp $
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*/
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#ifndef __IOSH7045_H
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#define __IOSH7045_H
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/*
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* After each line is explained whether the access is char short or long.
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* The functions read/writeb, w, l, 8, 16, 32 can be found
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* in exec/score/cpu/sh/sh_io.h
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*
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* 8 bit == char ( readb, writeb, read8, write8)
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* 16 bit == short ( readw, writew, read16, write16 )
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* 32 bit == long ( readl, writel, read32, write32 )
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* JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
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* ENGINE_..Hardware_Manual; alignment access-restrictions may apply
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*/
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#define REG_BASE 0xFFFF8000
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/* SCI0 Registers */
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#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
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#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
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#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
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#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
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#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
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#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
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/* SCI1 Registers */
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#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
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#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
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#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
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#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
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#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
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#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
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/* ADI */
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/* High Speed A/D (Excluding A-Mask Part)*/
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#define ADDRA (REG_BASE + 0x03F0) /* short */
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#define ADDRB (REG_BASE + 0x03F2) /* short */
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#define ADDRC (REG_BASE + 0x03F4) /* short */
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#define ADDRD (REG_BASE + 0x03F6) /* short */
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#define ADDRE (REG_BASE + 0x03F8) /* short */
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#define ADDRF (REG_BASE + 0x03FA) /* short */
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#define ADDRG (REG_BASE + 0x03FC) /* short */
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#define ADDRH (REG_BASE + 0x03FE) /* short */
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#define ADCSR (REG_BASE + 0x03E0) /* char */
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#define ADCR (REG_BASE + 0x03E1) /* char */
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/* Mid-Speed A/D (A-Mask part)*/
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#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
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#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
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#define ADDRA0L (REG_BASE + 0x0401) /* char */
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#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
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#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
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#define ADDRB0L (REG_BASE + 0x0403) /* char */
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#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
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#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
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#define ADDRC0L (REG_BASE + 0x0405) /* char */
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#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
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#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
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#define ADDRD0L (REG_BASE + 0x0407) /* char */
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#define ADCSR0 (REG_BASE + 0x0410) /* char */
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#define ADCR0 (REG_BASE + 0x0412) /* char */
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#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
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#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
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#define ADDRA1L (REG_BASE + 0x0409) /* char */
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#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
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#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
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#define ADDRB1L (REG_BASE + 0x040B) /* char */
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#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
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#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
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#define ADDRC1L (REG_BASE + 0x040D) /* char */
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#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
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#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
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#define ADDRD1L (REG_BASE + 0x040F) /* char */
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#define ADCSR1 (REG_BASE + 0x0411) /* char */
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#define ADCR1 (REG_BASE + 0x0413) /* char */
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/*MTU SHARED*/
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#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
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#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
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#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
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#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
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/*MTU CHANNEL 0*/
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#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
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#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
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#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
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#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
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#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
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#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
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#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
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#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
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#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
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#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
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#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
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/*MTU CHANNEL 1*/
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#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
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#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
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#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
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#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
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#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
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#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
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#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
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#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
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/*MTU CHANNEL 2*/
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#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
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#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
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#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
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#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
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#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
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#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
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#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
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#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
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/*MTU CHANNELS 3-4 SHARED*/
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#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
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#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
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#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
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#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
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#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
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#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
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#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
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/*MTU CHANNEL 3*/
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#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
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#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
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#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
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#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
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#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
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#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
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#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
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#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
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#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
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#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
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#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
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/*MTU CHANNEL 4*/
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#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
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#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
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#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
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#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
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#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
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#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
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#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
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#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
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#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
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#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
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#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
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#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
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/*DMAC CHANNELS 0-3 SHARED*/
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#define DMAOR (REG_BASE + 0x06B0) /* short */
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/*DMAC CHANNEL 0*/
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#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
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#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
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#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
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#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
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/*DMAC CHANNEL 1*/
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#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
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#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
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#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
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#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
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/*DMAC CHANNEL 3*/
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#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
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#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
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#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
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#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
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/*DMAC CHANNEL 4*/
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#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
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#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
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#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
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#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
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/*Data Transfer Controller*/
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#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
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#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
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#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
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#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
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#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
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#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
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#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
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/*Cache Memory*/
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#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
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/*INTC*/
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#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
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#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
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#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
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#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
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#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
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#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
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#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
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#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
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#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
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#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
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/*Flash (F-ZTAT)*/
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#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
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#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
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#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
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#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
|
| 252 |
|
|
#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
|
| 253 |
|
|
|
| 254 |
|
|
/*UBC*/
|
| 255 |
|
|
#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
|
| 256 |
|
|
#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
|
| 257 |
|
|
#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
|
| 258 |
|
|
#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
|
| 259 |
|
|
#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
|
| 260 |
|
|
/*BSC*/
|
| 261 |
|
|
#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
|
| 262 |
|
|
#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
|
| 263 |
|
|
#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
|
| 264 |
|
|
#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
|
| 265 |
|
|
#define BSC_DCR (REG_BASE + 0x062A) /* short */
|
| 266 |
|
|
#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
|
| 267 |
|
|
#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
|
| 268 |
|
|
#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
|
| 269 |
|
|
|
| 270 |
|
|
/*WDT*/
|
| 271 |
|
|
#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
|
| 272 |
|
|
#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
|
| 273 |
|
|
#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
|
| 274 |
|
|
#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
|
| 275 |
|
|
#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
|
| 276 |
|
|
#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
|
| 277 |
|
|
|
| 278 |
|
|
/*POWER DOWN STATE*/
|
| 279 |
|
|
#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
|
| 280 |
|
|
|
| 281 |
|
|
/* Port I/O Control Registers */
|
| 282 |
|
|
#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
|
| 283 |
|
|
#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
|
| 284 |
|
|
#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
|
| 285 |
|
|
#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
|
| 286 |
|
|
#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
|
| 287 |
|
|
#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
|
| 288 |
|
|
#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
|
| 289 |
|
|
#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
|
| 290 |
|
|
|
| 291 |
|
|
/*Pin Function Control Register*/
|
| 292 |
|
|
#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
|
| 293 |
|
|
#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
|
| 294 |
|
|
#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
|
| 295 |
|
|
#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
|
| 296 |
|
|
#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
|
| 297 |
|
|
#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
|
| 298 |
|
|
#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
|
| 299 |
|
|
#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
|
| 300 |
|
|
#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
|
| 301 |
|
|
#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
|
| 302 |
|
|
#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
|
| 303 |
|
|
#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
|
| 304 |
|
|
#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
|
| 305 |
|
|
#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
|
| 306 |
|
|
#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
|
| 307 |
|
|
#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
|
| 308 |
|
|
#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
|
| 309 |
|
|
#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
|
| 310 |
|
|
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
|
| 311 |
|
|
|
| 312 |
|
|
/*Compare/Match Timer*/
|
| 313 |
|
|
#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
|
| 314 |
|
|
#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
|
| 315 |
|
|
#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
|
| 316 |
|
|
#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
|
| 317 |
|
|
#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
|
| 318 |
|
|
#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
|
| 319 |
|
|
#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
|
| 320 |
|
|
|
| 321 |
|
|
#endif
|
