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#
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# $Id: README,v 1.2 2001-09-27 11:59:30 chris Exp $
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#
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This file discusses SPARC specific issues which are important to
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this port. The primary topics in this file are:
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+ Global Register Usage
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+ Stack Frame
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+ EF bit in the PSR
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Global Register Usage
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=====================
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This information on register usage is based heavily on a comment in the
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file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source.
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+ g0 is hardwired to 0
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+ On non-v9 systems:
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- g1 is free to use as temporary.
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- g2-g4 are reserved for applications. Gcc normally uses them as
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temporaries, but this can be disabled via the -mno-app-regs option.
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- g5 through g7 are reserved for the operating system.
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+ On v9 systems:
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- g1 and g5 are free to use as temporaries.
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- g2-g4 are reserved for applications (the compiler will not normally use
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them, but they can be used as temporaries with -mapp-regs).
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- g6-g7 are reserved for the operating system.
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NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios:
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+ as a temporary by the 64 bit sethi pattern
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+ when restoring call-preserved registers in large stack frames
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RTEMS places no constraints on the usage of the global registers. Although
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gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the
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operating system, RTEMS does not assume any special use for them.
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Stack Frame
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===========
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The stack grows downward (i.e. to lower addresses) on the SPARC architecture.
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The following is the organization of the stack frame:
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| ............... |
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fp | |
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+-------------------------------+
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| Local registers, temporaries, |
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| and saved floats | x bytes
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sp + x +-------------------------------+
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| outgoing parameters past |
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| the sixth one | x bytes
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sp + 92 +-------------------------------+ *
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| | *
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| area for callee to save | *
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| register arguments | * 24 bytes
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| | *
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sp + 68 +-------------------------------+ *
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| | *
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| structure return pointer | * 4 bytes
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| | *
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sp + 64 +-------------------------------+ *
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| | *
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| local register set | * 32 bytes
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| | *
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sp + 32 +-------------------------------+ *
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| | *
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| input register set | * 32 bytes
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sp +-------------------------------+ *
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* = minimal stack frame
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x = optional components
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EF bit in the PSR
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=================
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The EF (enable floating point unit) in the PSR is utilized in this port to
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prevent non-floating point tasks from performing floating point
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operations. This bit is maintained as part of the integer context.
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However, the floating point context is switched BEFORE the integer
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context. Thus the EF bit in place at the time of the FP switch may
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indicate that FP operations are disabled. This occurs on certain task
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switches, when the EF bit will be 0 for the outgoing task and thus a fault
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will be generated on the first FP operation of the FP context save.
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The remedy for this is to enable FP access as the first step in both the
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save and restore of the FP context area. This bit will be subsequently
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reloaded by the integer context switch.
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Two of the scenarios which demonstrate this problem are outlined below:
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1. When the first FP task is switched to. The system tasks are not FP and
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thus would be unable to restore the FP context of the incoming task.
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2. On a deferred FP context switch. In this case, the system might switch
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from FP Task A to non-FP Task B and then to FP Task C. In this scenario,
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the floating point state must technically be saved by a non-FP task.
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