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; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                Initialization values for registers after RESET
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  /* $Id: amd.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */
;
;* File information and includes.
 
        .file   "amd.ah"
        .ident  "@(#)amd.ah     1.1 96/05/23 08:56:58, TEI"
 
 
 
;
;* AMD PROCESSOR SPECIFIC VALUES...
;
 
;
;* Processor revision levels...
;
 
; PRL values: 31-28   27-24
; Am29000       0        x
; Am29005       1       x
; Am29050       2       x
; Am29035       3       x
; Am29030       4       x
; Am29200       5       x
; Am29205       5       1x
; Am29240       6       0
; Manx          7       0
; Cougar        8       0
 
 
        .equ    AM29000_PRL,    0x00
 
        .equ    AM29005_PRL,    0x10
 
        .equ    AM29050_PRL,    0x20
 
        .equ    AM29035_PRL,    0x30
 
        .equ    AM29030_PRL,    0x40
 
        .equ    AM29200_PRL,    0x50
 
        .equ    AM29205_PRL,    0x58
 
        .equ    AM29240_PRL,    0x60
 
        .equ    AM29040_PRL,    0x70
 
        .equ    MANX_PRL,       0x70
 
        .equ    COUGAR_PRL,     0x80
 
;
;* data structures sizes.
;
        .equ    CFGINFO_SIZE,   16*4
 
        .equ    PGMINFO_SIZE,   16*4
 
        .equ    VARARGS_SPACE,  16*4
 
        .equ    WINDOWSIZE,     0x80
;
;* Am29027 Mode registers
;
 
        .equ    Am29027Mode1, 0x0fc00820
 
        .equ    Am29027Mode2, 0x00001375
 
 
 
;* Processor Based Equates and Defines
 
        .equ    SIG_SYNC,       -1
 
        .equ    ENABLE,         (SM)
 
        .equ    DISABLE,        (ENABLE | DI | DA)
 
        .equ    DISABLE_FZ,     (FZ | ENABLE | DI | DA)
 
        .equ    CLR_TRAP,       (FZ | DA)
 
        .equ    InitOPS,        (TD | SM | (3<
 
        .equ    InitCPS,        (TD | SM | (0<
 
        .equ    InitCPS1,       (TD | SM | (0<
 
        .equ    CPS_TMR,        (SM | (0<
 
        .equ    CPS_INT0,       (TD | SM | (0<
 
        .equ    CPS_TMRINT0,    (SM | (0<
 
        .equ    InitCFG,        0x0
 
        .equ    InitRBP,        (B0|B1|B2|B3|B4|B5)
 
        .equ    TMC_VALUE,      0xFFFFFF
 
        .equ    TMR_VALUE,      (IE | TMC_VALUE)
 
 
 
 
 
 
;* 29205 specific (internal) peripheral initialization constants.
 
; Current Processor Status (CPS) Register.
; Old Processor Status Register (OPS).
 
        .equ    DA,     0x00001
        .equ    DI,     0x00002
        .equ    IMShift,0x2
        .equ    SM,     0x00010
        .equ    PI,     0x00020
        .equ    PD,     0x00040
        .equ    WM,     0x00080
        .equ    RE,     0x00100
        .equ    LK,     0x00200
        .equ    FZ,     0x00400
        .equ    TU,     0x00800
        .equ    TP,     0x01000
        .equ    TE,     0x02000
        .equ    IP,     0x04000
        .equ    CA,     0x08000
        .equ    MM,     0x10000
        .equ    TD,     0x20000
 
; Configuration Register (CFG)
 
        .equ    CD,     0x01
        .equ    CP,     0x02
        .equ    BO,     0x04
        .equ    RV,     0x08
        .equ    VF,     0x10
        .equ    DW,     0x20
        .equ    CO,     0x40
        .equ    EE,     0x80
        .equ    IDShift,        8
        .equ    CFG_ID, 0x100
        .equ    ILShift,        9
        .equ    CFG_ILMask,     0x600
        .equ    DDShift,        11
        .equ    CFG_DD, 0x800
        .equ    DLShift,        12
        .equ    CFG_DLMask,     0x3000
        .equ    PCEShift,       14
        .equ    CFG_PCE,        0x4000
        .equ    PMBShift,       16
        .equ    D16,    0x8000
        .equ    TBOShift,       23
        .equ    PRLShift, 24
 
; Channel Control Register (CHC)
 
        .equ    CV, 0x1
        .equ    NN, 0x2
        .equ    TRShift, 2
        .equ    TF, 0x400
        .equ    PER, 0x800
        .equ    LA, 0x1000
        .equ    ST, 0x2000
        .equ    ML, 0x4000
        .equ    LS, 0x8000
        .equ    CRShift, 16
        .equ    CNTLShift, 24
        .equ    CEShift, 31
        .equ    WBERShift, 31
 
; Register Bank Protect (RBP)
        .equ    B0, 0x1
        .equ    B1, 0x2
        .equ    B2, 0x4
        .equ    B3, 0x8
        .equ    B4, 0x10
        .equ    B5, 0x20
        .equ    B6, 0x40
        .equ    B7, 0x80
        .equ    B8, 0x100
        .equ    B9, 0x200
        .equ    B10, 0x400
        .equ    B11, 0x800
        .equ    B12, 0x1000
        .equ    B13, 0x2000
        .equ    B14, 0x4000
        .equ    B15, 0x8000
 
; Timer Counter
 
        .equ    TCVMask, 0xffffff
 
; Timer Reload Register
 
        .equ    IE, 0x1000000
        .equ    IN, 0x2000000
        .equ    OV, 0x4000000
        .equ    TRVMAsk, 0xffffff
 
; MMU Configuration
 
        .equ    PSShift, 8
        .equ    PS0Shift, 8
        .equ    PS1Shift, 12
 
; LRU Recommendation (LRU)
        .equ    LRUMask, 0xff
 
; Reason Vector (RSN)
        .equ    RSNMask, 0xff
 
; Region Mapping Address (RMA0 | RMA1)
        .equ    PBAMask,0xffff
        .equ    VBAShift, 16
 
; Region Mapping Control (RMC0 | RMC1)
        .equ    TIDMask, 0xff
        .equ    RMC_UE, 0x100
        .equ    RMC_UW, 0x200
        .equ    RMC_UR, 0x400
        .equ    RMC_SE, 0x800
        .equ    RMC_SW, 0x1000
        .equ    RMC_SR, 0x2000
        .equ    RMC_VE, 0x4000
        .equ    RMC_IO, 0x10000
        .equ    RGSShift, 17
        .equ    RMC_PGMShift, 22
 
; Instruction breakpoint Control (IBC0 | IBC1)
        .equ    BPIDMask, 0xff
        .equ    BTE, 0x100
        .equ    BRM, 0x200
        .equ    IBC_BSY, 0x400
        .equ    BEN, 0x800
        .equ    BHO, 0x1000
 
; Cache Data Register (CDR)
        .equ    CDR_US, 0x1
        .equ    P, 0x2
        .equ    CDR_V, 0x4
        .equ    IATAGShift, 20
 
; Cache Interface Register (CIR)
        .equ    CPTRShift, 2
        .equ    CIR_RW, 0x1000000
        .equ    FSELShift, 28
 
; Indirect Pointer A, B, C (IPA, IPB, IPC)
        .equ    IPShift, 2
 
; ALU Status (ALU)
        .equ    FCMask, 0x1F
        .equ    BPShift, 5
        .equ    C, 0x80
        .equ    Z, 0x100
        .equ    N, 0x200
        .equ    ALU_V, 0x400
        .equ    DF, 0x800
 
; Byte Pointer
        .equ    BPMask, 0x3
 
; Load/Store Count Remaining (CR)
        .equ    CRMask, 0xff
 
; Floating Point Environment (FPE)
        .equ    NM, 0x1
        .equ    RM, 0x2
        .equ    VM, 0x4
        .equ    UM, 0x8
        .equ    XM, 0x10
        .equ    DM, 0x20
        .equ    FRMShift, 6
        .equ    FF, 0x100
        .equ    ACFShift, 9
 
; Integer Environment (INTE)
        .equ    MO, 0x1
        .equ    DO, 0x2
 
; Floating Point Status (FPS)
        .equ    NS, 0x1
        .equ    RS, 0x2
        .equ    VS, 0x4
        .equ    FPS_US, 0x8
        .equ    XS, 0x10
        .equ    DS, 0x20
        .equ    NT, 0x100
        .equ    RT, 0x200
        .equ    VT, 0x400
        .equ    UT, 0x800
        .equ    XT, 0x1000
        .equ    DT, 0x2000
 
; Exception Opcode (EXOP)
        .equ    IOPMask, 0xff
 
; TLB Entry Word 0
;       .equ    TIDMask, 0xff   already defined above
        .equ    TLB_UE, 0x100
        .equ    TLB_UW, 0x200
        .equ    TLB_UR, 0x400
        .equ    TLB_SE, 0x800
        .equ    TLB_SW, 0x1000
        .equ    TLB_SR, 0x2000
        .equ    TLB_VE, 0x4000
        .equ    VTAGShift, 15
 
; TLB Entry Word 1
        .equ    TLB_IO, 0x1
        .equ    U, 0x2
        .equ    TLB_PGMShift, 6
        .equ    RPNShift, 10
 
; Am29200 ROM Control bits.
        .equ    RMCT_DW0Shift, 29
        .equ    RMCT_DW1Shift, 21
        .equ    RMCT_DW2Shift, 13
        .equ    RMCT_DW3Shift, 5
 
; Am29200 DRAM Control bits.
        .equ    DW3, (1<<18)
        .equ    DW2, (1<<22)
        .equ    DW1, (1<<26)
        .equ    DW0, (1<<30)
 
        ; Internal peripheral address assignments.
        .equ    RMCT, 0x80000000
        .equ    RMCF, 0x80000004
        .equ    DRCT, 0x80000008
        .equ    DRCF, 0x8000000C
        .equ    DRM0, 0x80000010
        .equ    DRM1, 0x80000014
        .equ    DRM2, 0x80000018
        .equ    DRM3, 0x8000001C
        .equ    PIACT0, 0x80000020
        .equ    PIACT1, 0x80000020
        .equ    ICT, 0x80000028
        .equ    DMCT0, 0x80000030
        .equ    DMAD0, 0x80000034
        .ifdef  revA
        .equ    TAD0, 0x80000036
        .equ    TCN0, 0x8000003A
        .else
        .equ    TAD0, 0x80000070        ; default
        .equ    TCN0, 0x8000003C        ; default
        .endif
        .equ    DMCN0, 0x80000038
        .equ    DMCT1, 0x80000040
        .equ    DMAD1, 0x80000044
        .equ    DMCN1, 0x80000048
        .equ    SPCT, 0x80000080
        .equ    SPST, 0x80000084
        .equ    SPTH, 0x80000088
        .equ    SPRB, 0x8000008C
        .equ    BAUD, 0x80000090
        .equ    PPCT, 0x800000C0
        .equ    PPST, 0x800000C1
        .equ    PPDT, 0x800000C4
        .equ    POCT, 0x800000D0
        .equ    PIN, 0x800000D4
        .equ    POUT, 0x800000D8
        .equ    POEN, 0x800000DC
        .equ    VCT, 0x800000E0
        .equ    TOP, 0x800000E4
        .equ    SIDE, 0x800000E8
        .equ    VDT, 0x800000EC
 
        ; Interrupt Controller Register bits.
        .equ    TXDI,   (1<<5)
        .equ    RXDI,   (1<<6)
        .equ    RXSI,   (1<<7)
        .equ    PPI,    (1<<11)
        .equ    DMA1I,  (1<<13)
        .equ    DMA0I,  (1<<14)
        .equ    IOPIMask,       (0xFF<<16)
        .equ    VDI,    (1<<27)
        .equ    ICT200_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
        .equ    ICT205_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
 
        ; Serial port Initialization bits
        .equ    NO_PARITY,      0
 
 
        ; SPST bits
        .equ    THREShift, 22
 
;* REGISTER Addresses
 
        .equ    ROMCntlRegAddr,         0x80000000
 
        .equ    ROMCfgRegAddr,          0x80000004
 
        .equ    DRAMCntlRegAddr,        0x80000008
 
        .equ    DRAMCfgRegAddr,         0x8000000C
 
        .equ    DRAMMap0RegAddr,        0x80000010
 
        .equ    DRAMMap1RegAddr,        0x80000014
 
        .equ    DRAMMap2RegAddr,        0x80000018
 
        .equ    DRAMMap3RegAddr,        0x8000001C
 
        .equ    PIACntl0RegAddr,        0x80000020
 
        .equ    PIACntl1RegAddr,        0x80000024
 
        .equ    INTRCntlRegAddr,        0x80000028
 
        .equ    DMACntl0RegAddr,        0x80000030
 
        .equ    DMACntl1RegAddr,        0x80000040
 
        .equ    SERPortCntlRegAddr,     0x80000080
 
        .equ    SERPortStatRegAddr,     0x80000084
 
        .equ    SERPortTHLDRegAddr,     0x80000088
 
        .equ    SERPortRbufRegAddr,     0x8000008C
 
        .equ    SERPortBaudRegAddr,     0x80000090
 
        .equ    PARPortCntlRegAddr,     0x800000C0
 
        .equ    PIOCntlRegAddr,         0x800000D0
 
        .equ    PIOInpRegAddr,          0x800000D4
 
        .equ    PIOOutRegAddr,          0x800000D8
 
        .equ    PIOOutEnaRegAddr,       0x800000DC
 
        .equ    VCTCntlRegAddr,         0x800000E0
 
;
;* Control constants
;
 
;* AM29030 Timer related constants.
 
        .equ    TMR_IE,                 0x01000000
 
        .equ    TMR_IN,                 0x02000000
 
        .equ    TMR_OV,                 0x04000000
 
        .equ    TMC_INITCNT,            1613
 
;
;* System initialization values.
;
 
        .equ    __os_version,           0x0001          ;
 
        .equ    STACKSize,              0x8000          ;
 
        .equ    PGMExecMode,            0x0000          ;
 
        .equ    TSTCK_OFST,             28 * 4
 
        .equ    CSTCK_OFST,             29 * 4
 
        .equ    TMSTCK_OFST,            30 * 4
 
        .equ    CMSTCK_OFST,            31 * 4
 
        .equ    CTXSW_OK,               0xA55A          ; ctx switch ok
 
        .set    NV_STARTOFST,           0x20            ; 32 bytes
 
        .set    NV_BAUDOFST,            0x00            ; 00 bytes
 
        .set    reg_cir,                29
 
        .set    reg_cdr,                30
 
        .equ    MSG_BUFSIZE,            0x1000          ; serial buffer size
 
        .equ    ILLOPTRAP,              0
 
        .equ    UATRAP,                 1
 
        .equ    PVTRAP,                 5
 
        .equ    UITLBMISSTRAP,          8
 
        .equ    UDTLBMISSTRAP,          9
 
        .equ    TIMERTRAP,              14
 
        .equ    TRACETRAP,              15
 
        .equ    XLINXTRAP,              16
 
        .equ    SERIALTRAP,             17
 
        .equ    SLOWTMRTRAP,            18
 
        .equ    PORTTRAP,               19
 
        .equ    SVSCTRAP,               80
 
        .equ    SVSCTRAP1,              81
 
        .equ    V_CACHETRAP,            66              ;
 
        .equ    V_SETSERVICE,           67              ;

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [amd.ah] - Blame information for rev 593

Line No.	Rev	Author	Line
1	30	unneback	`; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */`
2			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
3			`; Initialization values for registers after RESET`
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; /* $Id: amd.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */`
6			`;`
7			`;* File information and includes.`
8
9			`.file "amd.ah"`
10			`.ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI"`
11
12
13
14			`;`
15			`;* AMD PROCESSOR SPECIFIC VALUES...`
16			`;`
17
18			`;`
19			`;* Processor revision levels...`
20			`;`
21
22			`; PRL values: 31-28 27-24`
23			`; Am29000 0 x`
24			`; Am29005 1 x`
25			`; Am29050 2 x`
26			`; Am29035 3 x`
27			`; Am29030 4 x`
28			`; Am29200 5 x`
29			`; Am29205 5 1x`
30			`; Am29240 6 0`
31			`; Manx 7 0`
32			`; Cougar 8 0`
33
34
35			`.equ AM29000_PRL, 0x00`
36
37			`.equ AM29005_PRL, 0x10`
38
39			`.equ AM29050_PRL, 0x20`
40
41			`.equ AM29035_PRL, 0x30`
42
43			`.equ AM29030_PRL, 0x40`
44
45			`.equ AM29200_PRL, 0x50`
46
47			`.equ AM29205_PRL, 0x58`
48
49			`.equ AM29240_PRL, 0x60`
50
51			`.equ AM29040_PRL, 0x70`
52
53			`.equ MANX_PRL, 0x70`
54
55			`.equ COUGAR_PRL, 0x80`
56
57			`;`
58			`;* data structures sizes.`
59			`;`
60			`.equ CFGINFO_SIZE, 16*4`
61
62			`.equ PGMINFO_SIZE, 16*4`
63
64			`.equ VARARGS_SPACE, 16*4`
65
66			`.equ WINDOWSIZE, 0x80`
67			`;`
68			`;* Am29027 Mode registers`
69			`;`
70
71			`.equ Am29027Mode1, 0x0fc00820`
72
73			`.equ Am29027Mode2, 0x00001375`
74
75
76
77			`;* Processor Based Equates and Defines`
78
79			`.equ SIG_SYNC, -1`
80
81			`.equ ENABLE, (SM)`
82
83			`.equ DISABLE, (ENABLE \| DI \| DA)`
84
85			`.equ DISABLE_FZ, (FZ \| ENABLE \| DI \| DA)`
86
87			`.equ CLR_TRAP, (FZ \| DA)`
88
89			`.equ InitOPS, (TD \| SM \| (3<`
90
91			`.equ InitCPS, (TD \| SM \| (0<`
92
93			`.equ InitCPS1, (TD \| SM \| (0<`
94
95			`.equ CPS_TMR, (SM \| (0<`
96
97			`.equ CPS_INT0, (TD \| SM \| (0<`
98
99			`.equ CPS_TMRINT0, (SM \| (0<`
100
101			`.equ InitCFG, 0x0`
102
103			`.equ InitRBP, (B0\|B1\|B2\|B3\|B4\|B5)`
104
105			`.equ TMC_VALUE, 0xFFFFFF`
106
107			`.equ TMR_VALUE, (IE \| TMC_VALUE)`
108
109
110
111
112
113
114			`;* 29205 specific (internal) peripheral initialization constants.`
115
116			`; Current Processor Status (CPS) Register.`
117			`; Old Processor Status Register (OPS).`
118
119			`.equ DA, 0x00001`
120			`.equ DI, 0x00002`
121			`.equ IMShift,0x2`
122			`.equ SM, 0x00010`
123			`.equ PI, 0x00020`
124			`.equ PD, 0x00040`
125			`.equ WM, 0x00080`
126			`.equ RE, 0x00100`
127			`.equ LK, 0x00200`
128			`.equ FZ, 0x00400`
129			`.equ TU, 0x00800`
130			`.equ TP, 0x01000`
131			`.equ TE, 0x02000`
132			`.equ IP, 0x04000`
133			`.equ CA, 0x08000`
134			`.equ MM, 0x10000`
135			`.equ TD, 0x20000`
136
137			`; Configuration Register (CFG)`
138
139			`.equ CD, 0x01`
140			`.equ CP, 0x02`
141			`.equ BO, 0x04`
142			`.equ RV, 0x08`
143			`.equ VF, 0x10`
144			`.equ DW, 0x20`
145			`.equ CO, 0x40`
146			`.equ EE, 0x80`
147			`.equ IDShift, 8`
148			`.equ CFG_ID, 0x100`
149			`.equ ILShift, 9`
150			`.equ CFG_ILMask, 0x600`
151			`.equ DDShift, 11`
152			`.equ CFG_DD, 0x800`
153			`.equ DLShift, 12`
154			`.equ CFG_DLMask, 0x3000`
155			`.equ PCEShift, 14`
156			`.equ CFG_PCE, 0x4000`
157			`.equ PMBShift, 16`
158			`.equ D16, 0x8000`
159			`.equ TBOShift, 23`
160			`.equ PRLShift, 24`
161
162			`; Channel Control Register (CHC)`
163
164			`.equ CV, 0x1`
165			`.equ NN, 0x2`
166			`.equ TRShift, 2`
167			`.equ TF, 0x400`
168			`.equ PER, 0x800`
169			`.equ LA, 0x1000`
170			`.equ ST, 0x2000`
171			`.equ ML, 0x4000`
172			`.equ LS, 0x8000`
173			`.equ CRShift, 16`
174			`.equ CNTLShift, 24`
175			`.equ CEShift, 31`
176			`.equ WBERShift, 31`
177
178			`; Register Bank Protect (RBP)`
179			`.equ B0, 0x1`
180			`.equ B1, 0x2`
181			`.equ B2, 0x4`
182			`.equ B3, 0x8`
183			`.equ B4, 0x10`
184			`.equ B5, 0x20`
185			`.equ B6, 0x40`
186			`.equ B7, 0x80`
187			`.equ B8, 0x100`
188			`.equ B9, 0x200`
189			`.equ B10, 0x400`
190			`.equ B11, 0x800`
191			`.equ B12, 0x1000`
192			`.equ B13, 0x2000`
193			`.equ B14, 0x4000`
194			`.equ B15, 0x8000`
195
196			`; Timer Counter`
197
198			`.equ TCVMask, 0xffffff`
199
200			`; Timer Reload Register`
201
202			`.equ IE, 0x1000000`
203			`.equ IN, 0x2000000`
204			`.equ OV, 0x4000000`
205			`.equ TRVMAsk, 0xffffff`
206
207			`; MMU Configuration`
208
209			`.equ PSShift, 8`
210			`.equ PS0Shift, 8`
211			`.equ PS1Shift, 12`
212
213			`; LRU Recommendation (LRU)`
214			`.equ LRUMask, 0xff`
215
216			`; Reason Vector (RSN)`
217			`.equ RSNMask, 0xff`
218
219			`; Region Mapping Address (RMA0 \| RMA1)`
220			`.equ PBAMask,0xffff`
221			`.equ VBAShift, 16`
222
223			`; Region Mapping Control (RMC0 \| RMC1)`
224			`.equ TIDMask, 0xff`
225			`.equ RMC_UE, 0x100`
226			`.equ RMC_UW, 0x200`
227			`.equ RMC_UR, 0x400`
228			`.equ RMC_SE, 0x800`
229			`.equ RMC_SW, 0x1000`
230			`.equ RMC_SR, 0x2000`
231			`.equ RMC_VE, 0x4000`
232			`.equ RMC_IO, 0x10000`
233			`.equ RGSShift, 17`
234			`.equ RMC_PGMShift, 22`
235
236			`; Instruction breakpoint Control (IBC0 \| IBC1)`
237			`.equ BPIDMask, 0xff`
238			`.equ BTE, 0x100`
239			`.equ BRM, 0x200`
240			`.equ IBC_BSY, 0x400`
241			`.equ BEN, 0x800`
242			`.equ BHO, 0x1000`
243
244			`; Cache Data Register (CDR)`
245			`.equ CDR_US, 0x1`
246			`.equ P, 0x2`
247			`.equ CDR_V, 0x4`
248			`.equ IATAGShift, 20`
249
250			`; Cache Interface Register (CIR)`
251			`.equ CPTRShift, 2`
252			`.equ CIR_RW, 0x1000000`
253			`.equ FSELShift, 28`
254
255			`; Indirect Pointer A, B, C (IPA, IPB, IPC)`
256			`.equ IPShift, 2`
257
258			`; ALU Status (ALU)`
259			`.equ FCMask, 0x1F`
260			`.equ BPShift, 5`
261			`.equ C, 0x80`
262			`.equ Z, 0x100`
263			`.equ N, 0x200`
264			`.equ ALU_V, 0x400`
265			`.equ DF, 0x800`
266
267			`; Byte Pointer`
268			`.equ BPMask, 0x3`
269
270			`; Load/Store Count Remaining (CR)`
271			`.equ CRMask, 0xff`
272
273			`; Floating Point Environment (FPE)`
274			`.equ NM, 0x1`
275			`.equ RM, 0x2`
276			`.equ VM, 0x4`
277			`.equ UM, 0x8`
278			`.equ XM, 0x10`
279			`.equ DM, 0x20`
280			`.equ FRMShift, 6`
281			`.equ FF, 0x100`
282			`.equ ACFShift, 9`
283
284			`; Integer Environment (INTE)`
285			`.equ MO, 0x1`
286			`.equ DO, 0x2`
287
288			`; Floating Point Status (FPS)`
289			`.equ NS, 0x1`
290			`.equ RS, 0x2`
291			`.equ VS, 0x4`
292			`.equ FPS_US, 0x8`
293			`.equ XS, 0x10`
294			`.equ DS, 0x20`
295			`.equ NT, 0x100`
296			`.equ RT, 0x200`
297			`.equ VT, 0x400`
298			`.equ UT, 0x800`
299			`.equ XT, 0x1000`
300			`.equ DT, 0x2000`
301
302			`; Exception Opcode (EXOP)`
303			`.equ IOPMask, 0xff`
304
305			`; TLB Entry Word 0`
306			`; .equ TIDMask, 0xff already defined above`
307			`.equ TLB_UE, 0x100`
308			`.equ TLB_UW, 0x200`
309			`.equ TLB_UR, 0x400`
310			`.equ TLB_SE, 0x800`
311			`.equ TLB_SW, 0x1000`
312			`.equ TLB_SR, 0x2000`
313			`.equ TLB_VE, 0x4000`
314			`.equ VTAGShift, 15`
315
316			`; TLB Entry Word 1`
317			`.equ TLB_IO, 0x1`
318			`.equ U, 0x2`
319			`.equ TLB_PGMShift, 6`
320			`.equ RPNShift, 10`
321
322			`; Am29200 ROM Control bits.`
323			`.equ RMCT_DW0Shift, 29`
324			`.equ RMCT_DW1Shift, 21`
325			`.equ RMCT_DW2Shift, 13`
326			`.equ RMCT_DW3Shift, 5`
327
328			`; Am29200 DRAM Control bits.`
329			`.equ DW3, (1<<18)`
330			`.equ DW2, (1<<22)`
331			`.equ DW1, (1<<26)`
332			`.equ DW0, (1<<30)`
333
334			`; Internal peripheral address assignments.`
335			`.equ RMCT, 0x80000000`
336			`.equ RMCF, 0x80000004`
337			`.equ DRCT, 0x80000008`
338			`.equ DRCF, 0x8000000C`
339			`.equ DRM0, 0x80000010`
340			`.equ DRM1, 0x80000014`
341			`.equ DRM2, 0x80000018`
342			`.equ DRM3, 0x8000001C`
343			`.equ PIACT0, 0x80000020`
344			`.equ PIACT1, 0x80000020`
345			`.equ ICT, 0x80000028`
346			`.equ DMCT0, 0x80000030`
347			`.equ DMAD0, 0x80000034`
348			`.ifdef revA`
349			`.equ TAD0, 0x80000036`
350			`.equ TCN0, 0x8000003A`
351			`.else`
352			`.equ TAD0, 0x80000070 ; default`
353			`.equ TCN0, 0x8000003C ; default`
354			`.endif`
355			`.equ DMCN0, 0x80000038`
356			`.equ DMCT1, 0x80000040`
357			`.equ DMAD1, 0x80000044`
358			`.equ DMCN1, 0x80000048`
359			`.equ SPCT, 0x80000080`
360			`.equ SPST, 0x80000084`
361			`.equ SPTH, 0x80000088`
362			`.equ SPRB, 0x8000008C`
363			`.equ BAUD, 0x80000090`
364			`.equ PPCT, 0x800000C0`
365			`.equ PPST, 0x800000C1`
366			`.equ PPDT, 0x800000C4`
367			`.equ POCT, 0x800000D0`
368			`.equ PIN, 0x800000D4`
369			`.equ POUT, 0x800000D8`
370			`.equ POEN, 0x800000DC`
371			`.equ VCT, 0x800000E0`
372			`.equ TOP, 0x800000E4`
373			`.equ SIDE, 0x800000E8`
374			`.equ VDT, 0x800000EC`
375
376			`; Interrupt Controller Register bits.`
377			`.equ TXDI, (1<<5)`
378			`.equ RXDI, (1<<6)`
379			`.equ RXSI, (1<<7)`
380			`.equ PPI, (1<<11)`
381			`.equ DMA1I, (1<<13)`
382			`.equ DMA0I, (1<<14)`
383			`.equ IOPIMask, (0xFF<<16)`
384			`.equ VDI, (1<<27)`
385			`.equ ICT200_I, (TXDI\|RXDI\|RXSI\|PPI\|DMA1I\|DMA0I\|IOPIMask\|VDI)`
386			`.equ ICT205_I, (TXDI\|RXDI\|RXSI\|PPI\|DMA1I\|DMA0I\|IOPIMask\|VDI)`
387
388			`; Serial port Initialization bits`
389			`.equ NO_PARITY, 0`
390
391
392			`; SPST bits`
393			`.equ THREShift, 22`
394
395			`;* REGISTER Addresses`
396
397			`.equ ROMCntlRegAddr, 0x80000000`
398
399			`.equ ROMCfgRegAddr, 0x80000004`
400
401			`.equ DRAMCntlRegAddr, 0x80000008`
402
403			`.equ DRAMCfgRegAddr, 0x8000000C`
404
405			`.equ DRAMMap0RegAddr, 0x80000010`
406
407			`.equ DRAMMap1RegAddr, 0x80000014`
408
409			`.equ DRAMMap2RegAddr, 0x80000018`
410
411			`.equ DRAMMap3RegAddr, 0x8000001C`
412
413			`.equ PIACntl0RegAddr, 0x80000020`
414
415			`.equ PIACntl1RegAddr, 0x80000024`
416
417			`.equ INTRCntlRegAddr, 0x80000028`
418
419			`.equ DMACntl0RegAddr, 0x80000030`
420
421			`.equ DMACntl1RegAddr, 0x80000040`
422
423			`.equ SERPortCntlRegAddr, 0x80000080`
424
425			`.equ SERPortStatRegAddr, 0x80000084`
426
427			`.equ SERPortTHLDRegAddr, 0x80000088`
428
429			`.equ SERPortRbufRegAddr, 0x8000008C`
430
431			`.equ SERPortBaudRegAddr, 0x80000090`
432
433			`.equ PARPortCntlRegAddr, 0x800000C0`
434
435			`.equ PIOCntlRegAddr, 0x800000D0`
436
437			`.equ PIOInpRegAddr, 0x800000D4`
438
439			`.equ PIOOutRegAddr, 0x800000D8`
440
441			`.equ PIOOutEnaRegAddr, 0x800000DC`
442
443			`.equ VCTCntlRegAddr, 0x800000E0`
444
445			`;`
446			`;* Control constants`
447			`;`
448
449			`;* AM29030 Timer related constants.`
450
451			`.equ TMR_IE, 0x01000000`
452
453			`.equ TMR_IN, 0x02000000`
454
455			`.equ TMR_OV, 0x04000000`
456
457			`.equ TMC_INITCNT, 1613`
458
459			`;`
460			`;* System initialization values.`
461			`;`
462
463			`.equ __os_version, 0x0001 ;`
464
465			`.equ STACKSize, 0x8000 ;`
466
467			`.equ PGMExecMode, 0x0000 ;`
468
469			`.equ TSTCK_OFST, 28 * 4`
470
471			`.equ CSTCK_OFST, 29 * 4`
472
473			`.equ TMSTCK_OFST, 30 * 4`
474
475			`.equ CMSTCK_OFST, 31 * 4`
476
477			`.equ CTXSW_OK, 0xA55A ; ctx switch ok`
478
479			`.set NV_STARTOFST, 0x20 ; 32 bytes`
480
481			`.set NV_BAUDOFST, 0x00 ; 00 bytes`
482
483			`.set reg_cir, 29`
484
485			`.set reg_cdr, 30`
486
487			`.equ MSG_BUFSIZE, 0x1000 ; serial buffer size`
488
489			`.equ ILLOPTRAP, 0`
490
491			`.equ UATRAP, 1`
492
493			`.equ PVTRAP, 5`
494
495			`.equ UITLBMISSTRAP, 8`
496
497			`.equ UDTLBMISSTRAP, 9`
498
499			`.equ TIMERTRAP, 14`
500
501			`.equ TRACETRAP, 15`
502
503			`.equ XLINXTRAP, 16`
504
505			`.equ SERIALTRAP, 17`
506
507			`.equ SLOWTMRTRAP, 18`
508
509			`.equ PORTTRAP, 19`
510
511			`.equ SVSCTRAP, 80`
512
513			`.equ SVSCTRAP1, 81`
514
515			`.equ V_CACHETRAP, 66 ;`
516
517			`.equ V_SETSERVICE, 67 ;`