URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [pswmacro.ah] - Blame information for rev 173

Details | Compare with Previous | View Log


; /* @(#)pswmacro.ah    1.1 96/05/23 08:56:58, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                macros: Do_install and init_TLB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  /* $Id: pswmacro.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */
 
;* File information and includes.
 
        .file   "macro.ah"
        .ident  "@(#)pswmacro.ah        1.1 96/05/23 08:56:58, TEI"
 
 
        .macro  CONST32, RegName, RegValue
                const   RegName, RegValue
                consth  RegName, RegValue
        .endm
 
        .macro  CONSTX, RegName, RegValue
                .if (RegValue) <= 0x0000ffff
                        const   RegName, RegValue
                .else
                        const   RegName, RegValue
                        consth  RegName, RegValue
                .endif
        .endm
 
        .macro  PRODEV, RegName
                srl     RegName, RegName, 24
        .endm
 
;
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
;
 
;* Assumes vector table address in v0
 
        .macro  _setvec, trapnum, trapaddr
                mfsr    v0, vab                 ;
                const   v2, trapnum             ;
                sll     v1, v2, 2               ;
                add     v1, v1, v0              ; v0 has location of vector tab
 
                const   v2, trapaddr            ;
                consth  v2, trapaddr            ;
                store   0, 0, v2, v1            ;
                nop                             ;
        .endm
 
        .macro  syscall, name
                const     tav, HIF_@name        ;
                asneq   V_SYSCALL, gr1, gr1     ;
                nop                             ;
                nop                             ;
        .endm
 
 
 
;* MACRO TO INSTALL VECTOR TABLE ENTRIES
 
        .macro  Do_Install, V_Number, V_Address
                const   lr4, V_Address
                consth  lr4, V_Address
                const   lr3, V_Number * 4
                consth  lr3, V_Number * 4
                call    lr0, V_Install
                nop
        .endm
 
        .macro  Do_InstallX, V_Number, V_Address
                const   lr4, V_Address
                consth  lr4, V_Address
                const   lr3, V_Number * 4
                consth  lr3, V_Number * 4
                call    lr0, V_InstallX
                nop
        .endm
 
 
 
; push a register onto the stack
        .macro  pushreg, reg, sp
        sub     sp, sp, 4               ; adjust stack pointer
        store   0, 0, reg, sp           ; push register
        .endm
 
        .macro  push, sp, reg
                sub     sp, sp, 4
                store   0, 0, reg, sp
        .endm
 
; pop the register from stack
        .macro  popreg, reg, sp
        load    0, 0, reg, sp           ; pop register
        add     sp, sp, 4               ; adjust stack pointer
        .endm
        .macro  pop, reg, sp
                load    0, 0, reg, sp
                add     sp, sp, 4
        .endm
 
; push a special register onto stack
        .macro  pushspcl, spcl, tmpreg, sp
        sub     sp, sp, 4               ; adjust stack pointer
        mfsr    tmpreg, spcl            ; get spcl reg
        store   0, 0, tmpreg, sp        ; push onto stack
        .endm
 
        .macro  pushsr, sp, reg, sreg
                mfsr    reg, sreg
                sub     sp, sp, 4
                store   0, 0, reg, sp
        .endm
 
; pop a special register from stack
        .macro  popspcl, spcl, tmpreg, sp
        load    0, 0, tmpreg, sp        ; pop from stack
        add     sp, sp, 4               ; adjust stack pointer
        mtsr    spcl, tmpreg            ; set spcl reg
        .endm
 
        .macro  popsr, sreg, reg, sp
                load    0, 0, reg, sp
                add     sp, sp, 4
                mtsr    sreg, reg
        .endm
 
;
; save freeze mode registers on memory stack.
;
 
        .macro  SaveFZState,    tmp1, tmp2
 
                ; save freeze mode registers.
 
                pushspcl pc0, tmp1, msp
                pushspcl pc1, tmp1, msp
                pushspcl alu, tmp1, msp
 
                pushspcl cha, tmp1, msp
                pushspcl chd, tmp1, msp
                pushspcl chc, tmp1, msp
 
                pushspcl ops, tmp1, msp
 
                ; turn freeze off
 
                const   tmp2, FZ
                mfsr    tmp1, cps
                andn    tmp1, tmp1, tmp2
                mtsr    cps, tmp1
        .endm
 
; restore freeze mode registers from memory stack.
 
        .macro  RestoreFZState, tmp1, tmp2
 
                ; turn freeze on
 
                const   tmp2, (FZ|DI|DA)
                mfsr    tmp1, cps
                or      tmp1, tmp1, tmp2
                mtsr    cps, tmp1
 
                ; restore freeze mode registers.
 
                popspcl ops, tmp1, msp
                popspcl chc, tmp1, msp
                popspcl chd, tmp1, msp
                popspcl cha, tmp1, msp
                popspcl alu, tmp1, msp
                popspcl pc1, tmp1, msp
                popspcl pc0, tmp1, msp
        .endm
 
;
;*
;
        .equ    WS,     512                             ; window size
        .equ    RALLOC, 4 * 4                           ; stack alloc for C
        .equ    SIGCTX_UM_SIZE, 40 * 4                  ;
        .equ    SIGCTX_RFB, (38) * 4                    ; user mode saved
        .equ    SIGCTX_SM_SIZE, 12 * 4                  ;
        .equ    SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE     ;
        .equ    SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE     ;
        .equ    SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE      ;
        .equ    SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE      ;
 
        .macro  sup_sv
                add     it2, trapreg, 0                 ; transfer signal #
                sub     msp, msp, 4                     ;
                store   0, 0, it2, msp                  ; save signal number
                sub     msp, msp, 4                     ; push gr1
 
                store   0, 0, gr1, msp                  ;
                sub     msp, msp, 4                     ; push rab
                store   0, 0, rab, msp                  ;
                const   it0, WS                         ; Window size
 
                sub     rab, rfb, it0                   ; set rab = rfb-512
                pushsr  msp, it0, PC0                   ; save program counter0
                pushsr  msp, it0, PC1                   ; save program counter1
                pushsr  msp, it0, PC2                   ; save program counter2
 
                pushsr  msp, it0, CHA                   ; save channel address
                pushsr  msp, it0, CHD                   ; save channel data
                pushsr  msp, it0, CHC                   ; save channel control
                pushsr  msp, it0, ALU                   ; save alu
 
                pushsr  msp, it0, OPS                   ; save ops
                sub     msp, msp, 4                     ;
                store   0, 0, tav, msp                  ; push tav
                mtsrim  chc, 0                          ; no loadm/storem
 
                mfsr    it0, ops                        ; get ops value
                const   it1, (TD | DI)                  ; disable interrupts
                consth  it1, (TD | DI)                  ; disable interrupts
                or      it0, it0, it1                   ; set bits
 
                mtsr    ops, it0                        ; set new ops
                const   it0, sigcode                    ; signal handler
                consth  it0, sigcode                    ; signal handler
                mtsr    pc1, it0                        ; store pc1
 
                add     it1, it0, 4                     ; next addr
                mtsr    pc0, it1                        ; store pc1 location
                iret                                    ; return
                nop                                     ; ALIGN
        .endm
 
        .macro  sig_return
                mfsr    it0, cps                        ; get processor status
                const   it1, FZ|DA                      ; Freeze + traps disable
                or      it0, it0, it1                   ; to set FZ+DA
                mtsr    cps, it0                        ; in freeze mode
 
                load    0, 0, tav, msp                  ; restore tav
                add     msp, msp, 4                     ;
 
                popsr   OPS,it0, msp                    ;
                popsr   ALU,it0, msp                    ;
                popsr   CHC,it0, msp                    ;
                popsr   CHD,it0, msp                    ;
 
                popsr   CHA,it0, msp                    ;
                popsr   PC2,it0, msp                    ;
                popsr   PC1,it0, msp                    ;
                popsr   PC0,it0, msp                    ;
 
                load    0, 0, rab, msp                  ;
                add     msp, msp, 4                     ;
                load    0, 0, it0, msp                  ;
                add     gr1, it0, 0                     ; pop rsp
 
                add     msp, msp, 8                     ; discount signal #
                iret
        .endm
 
        .macro  repair_R_stack
                add     v0, msp, SIGCTX_GR1             ; interrupted gr1
                load    0, 0, v2, v0                    ;
                add     v0, msp, SIGCTX_RFB             ;
                load    0, 0, v3, v0                    ; interupted rfb
 
                const   v1, WS                          ;
                sub     v1, v3, v1                      ; rfb-512
                cpltu   v0, v2, v1                      ; test gr1 < rfb-512
                jmpf    v0, $1                          ;
 
                add     gr1, rab, 0                     ;
                add     v2, v1, 0                       ; set LB = rfb-512
$1:
;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
;* if no, LB=gr1 interrupted cache < 126 registers
                cpleu   v0, v2, rfb                     ; test LB<=rfb
                jmpf    v0, $2                          ;
                nop                                     ;
                add     v2, rfb, 0                      ;
$2:
                cpeq    v0, v3, rfb                     ; fill rfb->'rfb
                jmpt    v0, $3                          ; if rfb==rfb'
                const   tav, (0x80<<2)                  ; prepare for fill
                or      tav, tav, v2                    ;
 
                mtsr    IPA, tav                        ; IPA=LA<<2
                sub     tav, v3, gr98                   ; cache fill LA->rfb
                srl     tav, tav, 2                     ; convert to words
                sub     tav, tav, 1                     ;
 
                mtsr    cr, tav                         ;
                loadm   0, 0, gr0, v2                   ; fill from LA->rfb
$3:
                add     rfb, v3, 0                      ; move rfb upto 'rfb
                sub     rab, v1, 0                      ; assign rab to rfb-512
 
                add     v0, msp, SIGCTX_GR1             ;
                load    0, 0, v2, v0                    ; v0 = interrupted gr1
                add     gr1, v2, 0                      ; move gr1 upto 'gr1
                nop                                     ;
        .endm
 
        .macro  repair_regs
                mtsrim  cr, 29 - 1                      ; to restore locals
                loadm   0, 0, v0, msp                   ;
                add     msp, msp, 29*4                  ;
                popsr   Q, tav, msp                     ;
 
                popsr   IPC, tav, msp                   ;
                popsr   IPB, tav, msp                   ;
                popsr   IPA, tav, msp                   ;
                pop     FPStat3, msp                    ; floating point regs
 
                pop     FPStat2, msp                    ; floating point regs
                pop     FPStat1, msp                    ; floating point regs
                pop     FPStat0, msp                    ; floating point regs
 
                add     msp, msp, 3*4                   ; R-stack repaired
        .endm
 
;
;*HIF related...
;
 
 
 
 
; send the message in bufaddr to Montip.
        .macro  SendMessageToMontip,    bufaddr
        const   lr2, bufaddr
$1:
        call    lr0, _msg_send
        consth  lr2, bufaddr
        cpeq    gr96, gr96, 0
        jmpf    gr96, $1
        const   lr2, bufaddr
        .endm
 
; build a HIF_CALL message in bufaddr to send to montip.
        .macro  BuildHIFCALLMsg,        bufaddr, tmp1, tmp2
        const   tmp1, bufaddr
        consth  tmp1, bufaddr
        const   tmp2, HIF_CALL_MSGCODE
        store   0, 0, tmp2, tmp1        ; msg code
        add     tmp1, tmp1, 4
        const   tmp2, HIF_CALL_MSGLEN
        store   0, 0, tmp2, tmp1        ; msg len
        add     tmp1, tmp1, 4
        store   0, 0, gr121, tmp1       ; service number
        add     tmp1, tmp1, 4
        store   0, 0, lr2, tmp1         ; lr2
        add     tmp1, tmp1, 4
        store   0, 0, lr3, tmp1         ; lr3
        add     tmp1, tmp1, 4
        store   0, 0, lr4, tmp1         ; lr4
        .endm
 
;
;*
;* All the funky AMD style macros go in here...simply for
;* compatility
;
;
  .macro        IMPORT, symbol
        .extern symbol
  .endm
 
  .macro        GLOBAL, symbol
        .global symbol
  .endm
 
  .macro        USESECT, name, type
        .sect   name, type
        .use    name
  .endm
 
  .macro        SECTION, name, type
        .sect   name, type
  .endm
 
 .macro FUNC, fname, lineno
        .global fname
fname:
 .endm
 
 .macro ENDFUNC, fname, lineno
 .endm
 
;*************************************LONG
 .macro LONG, varname
varname:
        .block  4
 .endm
 
;*************************************UNSIGNED LONG
 .macro ULONG, varname
varname:
        .block  4
 .endm
 
;*************************************SHORT
 .macro SHORT, varname
varname:
        .block  2
 .endm
 
;*************************************CHAR
 .macro CHAR, varname
varname:
        .block  1
 .endm
 
;*************************************LONGARRAY
 .macro LONGARRAY, name, count
name:
        .block  count*4
 .endm
 
;*************************************SHORTARRAY
 
 .macro SHORTARRAY, name, count
name:
        .block  count*2
 .endm
 
;*************************************CHARARRAY
 
 .macro CHARARRAY, name, count
name:
        .block  count
 .endm
 
 
;*************************************VOID_FPTR
 
 .macro VOID_FPTR, name
name:
        .block  4
 .endm

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [pswmacro.ah] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */`
2			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
3			`; macros: Do_install and init_TLB`
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; /* $Id: pswmacro.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */`
6
7			`;* File information and includes.`
8
9			`.file "macro.ah"`
10			`.ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"`
11
12
13			`.macro CONST32, RegName, RegValue`
14			`const RegName, RegValue`
15			`consth RegName, RegValue`
16			`.endm`
17
18			`.macro CONSTX, RegName, RegValue`
19			`.if (RegValue) <= 0x0000ffff`
20			`const RegName, RegValue`
21			`.else`
22			`const RegName, RegValue`
23			`consth RegName, RegValue`
24			`.endif`
25			`.endm`
26
27			`.macro PRODEV, RegName`
28			`srl RegName, RegName, 24`
29			`.endm`
30
31			`;`
32			`;* MACRO TO INSTALL VECTOR TABLE ENTRIES`
33			`;`
34
35			`;* Assumes vector table address in v0`
36
37			`.macro _setvec, trapnum, trapaddr`
38			`mfsr v0, vab ;`
39			`const v2, trapnum ;`
40			`sll v1, v2, 2 ;`
41			`add v1, v1, v0 ; v0 has location of vector tab`
42
43			`const v2, trapaddr ;`
44			`consth v2, trapaddr ;`
45			`store 0, 0, v2, v1 ;`
46			`nop ;`
47			`.endm`
48
49			`.macro syscall, name`
50			`const tav, HIF_@name ;`
51			`asneq V_SYSCALL, gr1, gr1 ;`
52			`nop ;`
53			`nop ;`
54			`.endm`
55
56
57
58			`;* MACRO TO INSTALL VECTOR TABLE ENTRIES`
59
60			`.macro Do_Install, V_Number, V_Address`
61			`const lr4, V_Address`
62			`consth lr4, V_Address`
63			`const lr3, V_Number * 4`
64			`consth lr3, V_Number * 4`
65			`call lr0, V_Install`
66			`nop`
67			`.endm`
68
69			`.macro Do_InstallX, V_Number, V_Address`
70			`const lr4, V_Address`
71			`consth lr4, V_Address`
72			`const lr3, V_Number * 4`
73			`consth lr3, V_Number * 4`
74			`call lr0, V_InstallX`
75			`nop`
76			`.endm`
77
78
79
80			`; push a register onto the stack`
81			`.macro pushreg, reg, sp`
82			`sub sp, sp, 4 ; adjust stack pointer`
83			`store 0, 0, reg, sp ; push register`
84			`.endm`
85
86			`.macro push, sp, reg`
87			`sub sp, sp, 4`
88			`store 0, 0, reg, sp`
89			`.endm`
90
91			`; pop the register from stack`
92			`.macro popreg, reg, sp`
93			`load 0, 0, reg, sp ; pop register`
94			`add sp, sp, 4 ; adjust stack pointer`
95			`.endm`
96			`.macro pop, reg, sp`
97			`load 0, 0, reg, sp`
98			`add sp, sp, 4`
99			`.endm`
100
101			`; push a special register onto stack`
102			`.macro pushspcl, spcl, tmpreg, sp`
103			`sub sp, sp, 4 ; adjust stack pointer`
104			`mfsr tmpreg, spcl ; get spcl reg`
105			`store 0, 0, tmpreg, sp ; push onto stack`
106			`.endm`
107
108			`.macro pushsr, sp, reg, sreg`
109			`mfsr reg, sreg`
110			`sub sp, sp, 4`
111			`store 0, 0, reg, sp`
112			`.endm`
113
114			`; pop a special register from stack`
115			`.macro popspcl, spcl, tmpreg, sp`
116			`load 0, 0, tmpreg, sp ; pop from stack`
117			`add sp, sp, 4 ; adjust stack pointer`
118			`mtsr spcl, tmpreg ; set spcl reg`
119			`.endm`
120
121			`.macro popsr, sreg, reg, sp`
122			`load 0, 0, reg, sp`
123			`add sp, sp, 4`
124			`mtsr sreg, reg`
125			`.endm`
126
127			`;`
128			`; save freeze mode registers on memory stack.`
129			`;`
130
131			`.macro SaveFZState, tmp1, tmp2`
132
133			`; save freeze mode registers.`
134
135			`pushspcl pc0, tmp1, msp`
136			`pushspcl pc1, tmp1, msp`
137			`pushspcl alu, tmp1, msp`
138
139			`pushspcl cha, tmp1, msp`
140			`pushspcl chd, tmp1, msp`
141			`pushspcl chc, tmp1, msp`
142
143			`pushspcl ops, tmp1, msp`
144
145			`; turn freeze off`
146
147			`const tmp2, FZ`
148			`mfsr tmp1, cps`
149			`andn tmp1, tmp1, tmp2`
150			`mtsr cps, tmp1`
151			`.endm`
152
153			`; restore freeze mode registers from memory stack.`
154
155			`.macro RestoreFZState, tmp1, tmp2`
156
157			`; turn freeze on`
158
159			`const tmp2, (FZ\|DI\|DA)`
160			`mfsr tmp1, cps`
161			`or tmp1, tmp1, tmp2`
162			`mtsr cps, tmp1`
163
164			`; restore freeze mode registers.`
165
166			`popspcl ops, tmp1, msp`
167			`popspcl chc, tmp1, msp`
168			`popspcl chd, tmp1, msp`
169			`popspcl cha, tmp1, msp`
170			`popspcl alu, tmp1, msp`
171			`popspcl pc1, tmp1, msp`
172			`popspcl pc0, tmp1, msp`
173			`.endm`
174
175			`;`
176			`;*`
177			`;`
178			`.equ WS, 512 ; window size`
179			`.equ RALLOC, 4 * 4 ; stack alloc for C`
180			`.equ SIGCTX_UM_SIZE, 40 * 4 ;`
181			`.equ SIGCTX_RFB, (38) * 4 ; user mode saved`
182			`.equ SIGCTX_SM_SIZE, 12 * 4 ;`
183			`.equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;`
184			`.equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;`
185			`.equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;`
186			`.equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;`
187			`.equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;`
188			`.equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;`
189			`.equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;`
190			`.equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;`
191			`.equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;`
192
193			`.macro sup_sv`
194			`add it2, trapreg, 0 ; transfer signal #`
195			`sub msp, msp, 4 ;`
196			`store 0, 0, it2, msp ; save signal number`
197			`sub msp, msp, 4 ; push gr1`
198
199			`store 0, 0, gr1, msp ;`
200			`sub msp, msp, 4 ; push rab`
201			`store 0, 0, rab, msp ;`
202			`const it0, WS ; Window size`
203
204			`sub rab, rfb, it0 ; set rab = rfb-512`
205			`pushsr msp, it0, PC0 ; save program counter0`
206			`pushsr msp, it0, PC1 ; save program counter1`
207			`pushsr msp, it0, PC2 ; save program counter2`
208
209			`pushsr msp, it0, CHA ; save channel address`
210			`pushsr msp, it0, CHD ; save channel data`
211			`pushsr msp, it0, CHC ; save channel control`
212			`pushsr msp, it0, ALU ; save alu`
213
214			`pushsr msp, it0, OPS ; save ops`
215			`sub msp, msp, 4 ;`
216			`store 0, 0, tav, msp ; push tav`
217			`mtsrim chc, 0 ; no loadm/storem`
218
219			`mfsr it0, ops ; get ops value`
220			`const it1, (TD \| DI) ; disable interrupts`
221			`consth it1, (TD \| DI) ; disable interrupts`
222			`or it0, it0, it1 ; set bits`
223
224			`mtsr ops, it0 ; set new ops`
225			`const it0, sigcode ; signal handler`
226			`consth it0, sigcode ; signal handler`
227			`mtsr pc1, it0 ; store pc1`
228
229			`add it1, it0, 4 ; next addr`
230			`mtsr pc0, it1 ; store pc1 location`
231			`iret ; return`
232			`nop ; ALIGN`
233			`.endm`
234
235			`.macro sig_return`
236			`mfsr it0, cps ; get processor status`
237			`const it1, FZ\|DA ; Freeze + traps disable`
238			`or it0, it0, it1 ; to set FZ+DA`
239			`mtsr cps, it0 ; in freeze mode`
240
241			`load 0, 0, tav, msp ; restore tav`
242			`add msp, msp, 4 ;`
243
244			`popsr OPS,it0, msp ;`
245			`popsr ALU,it0, msp ;`
246			`popsr CHC,it0, msp ;`
247			`popsr CHD,it0, msp ;`
248
249			`popsr CHA,it0, msp ;`
250			`popsr PC2,it0, msp ;`
251			`popsr PC1,it0, msp ;`
252			`popsr PC0,it0, msp ;`
253
254			`load 0, 0, rab, msp ;`
255			`add msp, msp, 4 ;`
256			`load 0, 0, it0, msp ;`
257			`add gr1, it0, 0 ; pop rsp`
258
259			`add msp, msp, 8 ; discount signal #`
260			`iret`
261			`.endm`
262
263			`.macro repair_R_stack`
264			`add v0, msp, SIGCTX_GR1 ; interrupted gr1`
265			`load 0, 0, v2, v0 ;`
266			`add v0, msp, SIGCTX_RFB ;`
267			`load 0, 0, v3, v0 ; interupted rfb`
268
269			`const v1, WS ;`
270			`sub v1, v3, v1 ; rfb-512`
271			`cpltu v0, v2, v1 ; test gr1 < rfb-512`
272			`jmpf v0, $1 ;`
273
274			`add gr1, rab, 0 ;`
275			`add v2, v1, 0 ; set LB = rfb-512`
276			`$1:`
277			`;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill`
278			`;* if no, LB=gr1 interrupted cache < 126 registers`
279			`cpleu v0, v2, rfb ; test LB<=rfb`
280			`jmpf v0, $2 ;`
281			`nop ;`
282			`add v2, rfb, 0 ;`
283			`$2:`
284			`cpeq v0, v3, rfb ; fill rfb->'rfb`
285			`jmpt v0, $3 ; if rfb==rfb'`
286			`const tav, (0x80<<2) ; prepare for fill`
287			`or tav, tav, v2 ;`
288
289			`mtsr IPA, tav ; IPA=LA<<2`
290			`sub tav, v3, gr98 ; cache fill LA->rfb`
291			`srl tav, tav, 2 ; convert to words`
292			`sub tav, tav, 1 ;`
293
294			`mtsr cr, tav ;`
295			`loadm 0, 0, gr0, v2 ; fill from LA->rfb`
296			`$3:`
297			`add rfb, v3, 0 ; move rfb upto 'rfb`
298			`sub rab, v1, 0 ; assign rab to rfb-512`
299
300			`add v0, msp, SIGCTX_GR1 ;`
301			`load 0, 0, v2, v0 ; v0 = interrupted gr1`
302			`add gr1, v2, 0 ; move gr1 upto 'gr1`
303			`nop ;`
304			`.endm`
305
306			`.macro repair_regs`
307			`mtsrim cr, 29 - 1 ; to restore locals`
308			`loadm 0, 0, v0, msp ;`
309			`add msp, msp, 29*4 ;`
310			`popsr Q, tav, msp ;`
311
312			`popsr IPC, tav, msp ;`
313			`popsr IPB, tav, msp ;`
314			`popsr IPA, tav, msp ;`
315			`pop FPStat3, msp ; floating point regs`
316
317			`pop FPStat2, msp ; floating point regs`
318			`pop FPStat1, msp ; floating point regs`
319			`pop FPStat0, msp ; floating point regs`
320
321			`add msp, msp, 3*4 ; R-stack repaired`
322			`.endm`
323
324			`;`
325			`;*HIF related...`
326			`;`
327
328
329
330
331			`; send the message in bufaddr to Montip.`
332			`.macro SendMessageToMontip, bufaddr`
333			`const lr2, bufaddr`
334			`$1:`
335			`call lr0, _msg_send`
336			`consth lr2, bufaddr`
337			`cpeq gr96, gr96, 0`
338			`jmpf gr96, $1`
339			`const lr2, bufaddr`
340			`.endm`
341
342			`; build a HIF_CALL message in bufaddr to send to montip.`
343			`.macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2`
344			`const tmp1, bufaddr`
345			`consth tmp1, bufaddr`
346			`const tmp2, HIF_CALL_MSGCODE`
347			`store 0, 0, tmp2, tmp1 ; msg code`
348			`add tmp1, tmp1, 4`
349			`const tmp2, HIF_CALL_MSGLEN`
350			`store 0, 0, tmp2, tmp1 ; msg len`
351			`add tmp1, tmp1, 4`
352			`store 0, 0, gr121, tmp1 ; service number`
353			`add tmp1, tmp1, 4`
354			`store 0, 0, lr2, tmp1 ; lr2`
355			`add tmp1, tmp1, 4`
356			`store 0, 0, lr3, tmp1 ; lr3`
357			`add tmp1, tmp1, 4`
358			`store 0, 0, lr4, tmp1 ; lr4`
359			`.endm`
360
361			`;`
362			`;*`
363			`;* All the funky AMD style macros go in here...simply for`
364			`;* compatility`
365			`;`
366			`;`
367			`.macro IMPORT, symbol`
368			`.extern symbol`
369			`.endm`
370
371			`.macro GLOBAL, symbol`
372			`.global symbol`
373			`.endm`
374
375			`.macro USESECT, name, type`
376			`.sect name, type`
377			`.use name`
378			`.endm`
379
380			`.macro SECTION, name, type`
381			`.sect name, type`
382			`.endm`
383
384			`.macro FUNC, fname, lineno`
385			`.global fname`
386			`fname:`
387			`.endm`
388
389			`.macro ENDFUNC, fname, lineno`
390			`.endm`
391
392			`;*************************************LONG`
393			`.macro LONG, varname`
394			`varname:`
395			`.block 4`
396			`.endm`
397
398			`;*************************************UNSIGNED LONG`
399			`.macro ULONG, varname`
400			`varname:`
401			`.block 4`
402			`.endm`
403
404			`;*************************************SHORT`
405			`.macro SHORT, varname`
406			`varname:`
407			`.block 2`
408			`.endm`
409
410			`;*************************************CHAR`
411			`.macro CHAR, varname`
412			`varname:`
413			`.block 1`
414			`.endm`
415
416			`;*************************************LONGARRAY`
417			`.macro LONGARRAY, name, count`
418			`name:`
419			`.block count*4`
420			`.endm`
421
422			`;*************************************SHORTARRAY`
423
424			`.macro SHORTARRAY, name, count`
425			`name:`
426			`.block count*2`
427			`.endm`
428
429			`;*************************************CHARARRAY`
430
431			`.macro CHARARRAY, name, count`
432			`name:`
433			`.block count`
434			`.endm`
435
436
437			`;*************************************VOID_FPTR`
438
439			`.macro VOID_FPTR, name`
440			`name:`
441			`.block 4`
442			`.endm`