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; /* @(#)register.s     1.1 96/05/23 08:57:34, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                Register Definitions and Usage Conventions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  /* $Id: register.S,v 1.2 2001-09-27 11:59:42 chris Exp $ */
;
 
;* File information and includes.
 
        .file   "c_register.s"
        .ident  "@(#)register.s 1.1 96/05/23 08:57:34, TEI\n"
 
; Basic guidelines for register distribution and usage are derived from
; the AMD application notes. It would be best to stick with the conventions
; laid out by AMD.
; Application Note: Context Switching with 29000 Processor By Daniel Mann.
 
;
;*************************************************************************
;
 
;
; Rule 1:
;       Gr1 is used as a pointer to the register stack
;       Lr1 is used as frame pointer
;
 
        .reg    regsp,          gr1             ; Register Stack Pointer
        .reg    fp,             lr1             ; frame pointer
 
        .equ    Rrsp,           ®sp
        .equ    Rfp,            &fp
 
        .global Rrsp, Rfp
 
;
;*************************************************************************
;
 
;
;       Gr2-Gr63 are not implemented in silicon
;
 
;
;*************************************************************************
;
 
;
; Rule 2:
; The registers GR64-GR95 are dedicated for operating system use.
;
 
; The  register range GR64-GR95 i.e 32 Registers  is furthur sub-divided as
; follows...
; gr64-gr67 interrupt handlers.
; gr68-gr71 OS temporaries I
; gr72-gr79 OS temporaries II
; gr80-gr95 OS statics. Dedicated throughout the operation of a program.
 
 
;
;       32 Registers for Operating System Use.
;
 
;
;       Assigning Names to Interrupt Handlers Registers.
;
 
        .reg    OSint0,         gr64
        .reg    OSint1,         gr65
        .reg    OSint2,         gr66
        .reg    OSint3,         gr67
 
        .equ    ROSint0,        &OSint0
        .equ    ROSint1,        &OSint1
        .equ    ROSint2,        &OSint2
        .equ    ROSint3,        &OSint3
 
        .global ROSint0, ROSint1, ROSint2, ROSint3
 
        .reg    TrapReg,        gr64            ; trap register
        .reg    trapreg,        gr64            ; trapreg
 
        .equ    RTrapReg,       &TrapReg
        .equ    Rtrapreg,       &trapreg
 
        .global RTrapReg, Rtrapreg
 
 
;
;       Assigning Names to Scratch/Temporary Registers.
;
 
        .reg    OStmp0,         gr68
        .reg    OStmp1,         gr69
        .reg    OStmp2,         gr70
        .reg    OStmp3,         gr71
 
        .reg    OStmp4,         gr72
        .reg    OStmp5,         gr73
        .reg    OStmp6,         gr74
        .reg    OStmp7,         gr75
 
        .reg    OStmp8,         gr76
        .reg    OStmp9,         gr77
        .reg    OStmp10,        gr78
        .reg    OStmp11,        gr79
 
        .equ    ROStmp0,        &OStmp0
        .equ    ROStmp1,        &OStmp1
        .equ    ROStmp2,        &OStmp2
        .equ    ROStmp3,        &OStmp3
 
        .equ    ROStmp4,        &OStmp4
        .equ    ROStmp5,        &OStmp5
        .equ    ROStmp6,        &OStmp6
        .equ    ROStmp7,        &OStmp7
 
        .equ    ROStmp8,        &OStmp8
        .equ    ROStmp9,        &OStmp9
        .equ    ROStmp10,       &OStmp10
        .equ    ROStmp11,       &OStmp11
 
        .global ROStmp0, ROStmp1, ROStmp2, ROStmp3
        .global ROStmp4, ROStmp5, ROStmp6, ROStmp7
        .global ROStmp8, ROStmp9, ROStmp10, ROStmp11
 
;
;       Assigning Names to Statics/Permanent Registers.
;
 
        .reg    OSsta0,         gr80            ; Spill Address Register
        .reg    OSsta1,         gr81            ; Fill Address Register
        .reg    OSsta2,         gr82            ; Signal Address Register
        .reg    OSsta3,         gr83            ; pcb Register
 
        .reg    OSsta4,         gr84            ;
        .reg    OSsta5,         gr85            ;
        .reg    OSsta6,         gr86            ;
        .reg    OSsta7,         gr87            ;
 
        .reg    OSsta8,         gr88            ;
        .reg    OSsta9,         gr89            ;
        .reg    OSsta10,        gr90            ;
        .reg    OSsta11,        gr91            ;
 
        .reg    OSsta12,        gr92            ;
        .reg    OSsta13,        gr93            ;
        .reg    OSsta14,        gr94            ;
        .reg    OSsta15,        gr95            ;
 
;
;       Round 2 of Name Assignments
;
 
;
;       Assignment of Specific Use oriented names to statics.
;
        .reg    SpillAddrReg,   gr80
        .reg    FillAddrReg,    gr81
        .reg    SignalAddrReg,  gr82
        .reg    pcb,            gr83
 
        .reg    etx,            gr80
        .reg    ety,            gr81
        .reg    etz,            gr82
        .reg    etc,            gr83
 
;*
 
        .reg    TimerExt,       gr84
        .reg    TimerUtil,      gr85
 
;*
 
        .reg    LEDReg,         gr86
        .reg    ERRReg,         gr87
 
        .reg    eta,            gr86
        .reg    etb,            gr87
 
;*
 
 
;* The following registers are used by switching code
 
        .reg    et0,            gr88
        .reg    et1,            gr89
        .reg    et2,            gr90
        .reg    et3,            gr91
 
        .reg    et4,            gr92
        .reg    et5,            gr93
        .reg    et6,            gr94
        .reg    et7,            gr95
 
 
; The floating point trap handlers need a few static registers
 
        .reg    FPStat0,        gr88
        .reg    FPStat1,        gr89
        .reg    FPStat2,        gr90
        .reg    FPStat3,        gr91
 
; The following registers are used temporarily during diagnostics.
 
        .reg    XLINXReg,       gr92
        .reg    VMBCReg,        gr93
        .reg    UARTReg,        gr94
        .reg    ETHERReg,       gr95
 
;*
 
;;*
        .reg    heapptr,        gr90
        .reg    ArgvPtr,        gr91
;;*
 
 
 
;
;*      Preparing to export Register Names for the Linkers benefit.
;
 
        .equ    RSpillAddrReg,  &SpillAddrReg
        .equ    RFillAddrReg,   &FillAddrReg
        .equ    RSignalAddrReg, &SignalAddrReg
        .equ    Rpcb,           &pcb
 
        .equ    Retx,           &etx
        .equ    Rety,           &ety
        .equ    Retz,           &etz
        .equ    Reta,           &eta
 
        .equ    Retb,           &etb
        .equ    Retc,           &etc
        .equ    RTimerExt,      &TimerExt
        .equ    RTimerUtil,     &TimerUtil
 
        .equ    RLEDReg,        &LEDReg
        .equ    RERRReg,        &ERRReg
 
        .equ    Ret0,           &et0
        .equ    Ret1,           &et1
        .equ    Ret2,           &et2
        .equ    Ret3,           &et3
 
        .equ    RFPStat0,       &FPStat0
        .equ    RFPStat1,       &FPStat1
        .equ    RFPStat2,       &FPStat2
        .equ    RFPStat3,       &FPStat3
 
        .equ    Rheapptr,       &heapptr
        .equ    RHeapPtr,       &heapptr
        .equ    RArgvPtr,       &ArgvPtr
 
        .equ    Ret4,           &et4
        .equ    Ret5,           &et5
        .equ    Ret6,           &et6
        .equ    Ret7,           &et7
 
        .equ    RXLINXReg,      &XLINXReg
        .equ    RVMBCReg,       &VMBCReg
        .equ    RUARTReg,       &UARTReg
        .equ    RETHERReg,      ÐERReg
 
        .global RSpillAddrReg, RFillAddrReg, RSignalAddrReg
        .global Rpcb, Retc
        .global RTimerExt, RTimerUtil, RLEDReg, RERRReg
        .global Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb
        .global Retx, Rety, Retz
        .global RFPStat0, RFPStat1, RFPStat2, RFPStat3
        .global Rheapptr, RHeapPtr, RArgvPtr
        .global RXLINXReg, RVMBCReg, RUARTReg, RETHERReg
 
;
;*************************************************************************
;
 
 
;
; Rule 3:
;       Gr96-Gr127 Compiler & Programmer use registers.
;       32 Registers for Compiler & Programmer use
 
;
;       16 Registers for Compiler Use.
;
 
;
;       Compiler Temporaries and Function Return Values
;
 
        .reg v0,                gr96            ; First word of Return Value
        .reg v1,                gr97
        .reg v2,                gr98
        .reg v3,                gr99
 
        .reg v4,                gr100
        .reg v5,                gr101
        .reg v6,                gr102
        .reg v7,                gr103
 
        .reg v8,                gr104
        .reg v9,                gr105
        .reg v10,               gr106
        .reg v11,               gr107
 
        .reg v12,               gr108
        .reg v13,               gr109
        .reg v14,               gr110
        .reg v15,               gr111
 
        .equ Rv0,               &v0
        .equ Rv1,               &v1
        .equ Rv2,               &v2
        .equ Rv3,               &v3
 
        .equ Rv4,               &v4
        .equ Rv5,               &v5
        .equ Rv6,               &v6
        .equ Rv7,               &v7
 
        .equ Rv8,               &v8
        .equ Rv9,               &v9
        .equ Rv10,              &v10
        .equ Rv11,              &v11
 
        .equ Rv12,              &v12
        .equ Rv13,              &v13
        .equ Rv14,              &v14
        .equ Rv15,              &v15
 
        .global Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9
        .global Rv10, Rv11, Rv12, Rv13, Rv14, Rv15
 
 
;
;       User Process Statics Registers
;
 
        .reg rp0,               gr112           ; Reserved for Programmer, #0
        .reg rp1,               gr113           ; Reserved for Programmer, #1
        .reg rp2,               gr114           ; Reserved for Programmer, #2
        .reg rp3,               gr115           ; Reserved for Programmer, #3
 
        .equ Rrp0,              &rp0
        .equ Rrp1,              &rp1
        .equ Rrp2,              &rp2
        .equ Rrp3,              &rp3
 
        .global Rrp0, Rrp1, Rrp2, Rrp3
 
;
;       Compiler Temporaries II
;
 
        .reg tv0,               gr116           ;
        .reg tv1,               gr117           ;
        .reg tv2,               gr118           ;
        .reg tv3,               gr119           ;
        .reg tv4,               gr120           ;
 
        .equ Rtv0,              &tv0		;
        .equ Rtv1,              &tv1		;
        .equ Rtv2,              &tv2		;
        .equ Rtv3,              &tv3		;
        .equ Rtv4,              &tv4		;
 
        .global Rtv0, Rtv1, Rtv2, Rtv3, Rtv4
 
;
;       Special pointers and registers for handlers and stack operations.
;
 
        .reg tav,               gr121           ; Temp, Arg for Trap Handlers
        .reg tpc,               gr122           ; Temp, Ret PC for Trap Handlers
        .reg lrp,               gr123           ; Large Return Pointer
        .reg slp,               gr124           ; Static Link Pointer
 
        .reg msp,               gr125           ; Memory Stack Pointer
        .reg rab,               gr126           ; Register Allocate Bound
        .reg rfb,               gr127           ; Register Free Bound
 
        .equ Rtav,              &tav
        .equ Rtpc,              &tpc
        .equ Rlrp,              &lrp
        .equ Rslp,              &slp
        .equ Rmsp,              &msp
        .equ Rrab,              &rab
        .equ Rrfb,              &rfb
 
        .global Rtav, Rtpc, Rlrp, Rslp, Rmsp, Rrab, Rrfb

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [register.S] - Blame information for rev 30

Line No.	Rev	Author	Line
1	30	unneback	`; /* @(#)register.s 1.1 96/05/23 08:57:34, TEI */`
2			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
3			`; Register Definitions and Usage Conventions`
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; /* $Id: register.S,v 1.2 2001-09-27 11:59:42 chris Exp $ */`
6			`;`
7
8			`;* File information and includes.`
9
10			`.file "c_register.s"`
11			`.ident "@(#)register.s 1.1 96/05/23 08:57:34, TEI\n"`
12
13			`; Basic guidelines for register distribution and usage are derived from`
14			`; the AMD application notes. It would be best to stick with the conventions`
15			`; laid out by AMD.`
16			`; Application Note: Context Switching with 29000 Processor By Daniel Mann.`
17
18			`;`
19			`;*************************************************************************`
20			`;`
21
22			`;`
23			`; Rule 1:`
24			`; Gr1 is used as a pointer to the register stack`
25			`; Lr1 is used as frame pointer`
26			`;`
27
28			`.reg regsp, gr1 ; Register Stack Pointer`
29			`.reg fp, lr1 ; frame pointer`
30
31			`.equ Rrsp, ®sp`
32			`.equ Rfp, &fp`
33
34			`.global Rrsp, Rfp`
35
36			`;`
37			`;*************************************************************************`
38			`;`
39
40			`;`
41			`; Gr2-Gr63 are not implemented in silicon`
42			`;`
43
44			`;`
45			`;*************************************************************************`
46			`;`
47
48			`;`
49			`; Rule 2:`
50			`; The registers GR64-GR95 are dedicated for operating system use.`
51			`;`
52
53			`; The register range GR64-GR95 i.e 32 Registers is furthur sub-divided as`
54			`; follows...`
55			`; gr64-gr67 interrupt handlers.`
56			`; gr68-gr71 OS temporaries I`
57			`; gr72-gr79 OS temporaries II`
58			`; gr80-gr95 OS statics. Dedicated throughout the operation of a program.`
59
60
61			`;`
62			`; 32 Registers for Operating System Use.`
63			`;`
64
65			`;`
66			`; Assigning Names to Interrupt Handlers Registers.`
67			`;`
68
69			`.reg OSint0, gr64`
70			`.reg OSint1, gr65`
71			`.reg OSint2, gr66`
72			`.reg OSint3, gr67`
73
74			`.equ ROSint0, &OSint0`
75			`.equ ROSint1, &OSint1`
76			`.equ ROSint2, &OSint2`
77			`.equ ROSint3, &OSint3`
78
79			`.global ROSint0, ROSint1, ROSint2, ROSint3`
80
81			`.reg TrapReg, gr64 ; trap register`
82			`.reg trapreg, gr64 ; trapreg`
83
84			`.equ RTrapReg, &TrapReg`
85			`.equ Rtrapreg, &trapreg`
86
87			`.global RTrapReg, Rtrapreg`
88
89
90			`;`
91			`; Assigning Names to Scratch/Temporary Registers.`
92			`;`
93
94			`.reg OStmp0, gr68`
95			`.reg OStmp1, gr69`
96			`.reg OStmp2, gr70`
97			`.reg OStmp3, gr71`
98
99			`.reg OStmp4, gr72`
100			`.reg OStmp5, gr73`
101			`.reg OStmp6, gr74`
102			`.reg OStmp7, gr75`
103
104			`.reg OStmp8, gr76`
105			`.reg OStmp9, gr77`
106			`.reg OStmp10, gr78`
107			`.reg OStmp11, gr79`
108
109			`.equ ROStmp0, &OStmp0`
110			`.equ ROStmp1, &OStmp1`
111			`.equ ROStmp2, &OStmp2`
112			`.equ ROStmp3, &OStmp3`
113
114			`.equ ROStmp4, &OStmp4`
115			`.equ ROStmp5, &OStmp5`
116			`.equ ROStmp6, &OStmp6`
117			`.equ ROStmp7, &OStmp7`
118
119			`.equ ROStmp8, &OStmp8`
120			`.equ ROStmp9, &OStmp9`
121			`.equ ROStmp10, &OStmp10`
122			`.equ ROStmp11, &OStmp11`
123
124			`.global ROStmp0, ROStmp1, ROStmp2, ROStmp3`
125			`.global ROStmp4, ROStmp5, ROStmp6, ROStmp7`
126			`.global ROStmp8, ROStmp9, ROStmp10, ROStmp11`
127
128			`;`
129			`; Assigning Names to Statics/Permanent Registers.`
130			`;`
131
132			`.reg OSsta0, gr80 ; Spill Address Register`
133			`.reg OSsta1, gr81 ; Fill Address Register`
134			`.reg OSsta2, gr82 ; Signal Address Register`
135			`.reg OSsta3, gr83 ; pcb Register`
136
137			`.reg OSsta4, gr84 ;`
138			`.reg OSsta5, gr85 ;`
139			`.reg OSsta6, gr86 ;`
140			`.reg OSsta7, gr87 ;`
141
142			`.reg OSsta8, gr88 ;`
143			`.reg OSsta9, gr89 ;`
144			`.reg OSsta10, gr90 ;`
145			`.reg OSsta11, gr91 ;`
146
147			`.reg OSsta12, gr92 ;`
148			`.reg OSsta13, gr93 ;`
149			`.reg OSsta14, gr94 ;`
150			`.reg OSsta15, gr95 ;`
151
152			`;`
153			`; Round 2 of Name Assignments`
154			`;`
155
156			`;`
157			`; Assignment of Specific Use oriented names to statics.`
158			`;`
159			`.reg SpillAddrReg, gr80`
160			`.reg FillAddrReg, gr81`
161			`.reg SignalAddrReg, gr82`
162			`.reg pcb, gr83`
163
164			`.reg etx, gr80`
165			`.reg ety, gr81`
166			`.reg etz, gr82`
167			`.reg etc, gr83`
168
169			`;*`
170
171			`.reg TimerExt, gr84`
172			`.reg TimerUtil, gr85`
173
174			`;*`
175
176			`.reg LEDReg, gr86`
177			`.reg ERRReg, gr87`
178
179			`.reg eta, gr86`
180			`.reg etb, gr87`
181
182			`;*`
183
184
185			`;* The following registers are used by switching code`
186
187			`.reg et0, gr88`
188			`.reg et1, gr89`
189			`.reg et2, gr90`
190			`.reg et3, gr91`
191
192			`.reg et4, gr92`
193			`.reg et5, gr93`
194			`.reg et6, gr94`
195			`.reg et7, gr95`
196
197
198			`; The floating point trap handlers need a few static registers`
199
200			`.reg FPStat0, gr88`
201			`.reg FPStat1, gr89`
202			`.reg FPStat2, gr90`
203			`.reg FPStat3, gr91`
204
205			`; The following registers are used temporarily during diagnostics.`
206
207			`.reg XLINXReg, gr92`
208			`.reg VMBCReg, gr93`
209			`.reg UARTReg, gr94`
210			`.reg ETHERReg, gr95`
211
212			`;*`
213
214			`;;*`
215			`.reg heapptr, gr90`
216			`.reg ArgvPtr, gr91`
217			`;;*`
218
219
220
221			`;`
222			`;* Preparing to export Register Names for the Linkers benefit.`
223			`;`
224
225			`.equ RSpillAddrReg, &SpillAddrReg`
226			`.equ RFillAddrReg, &FillAddrReg`
227			`.equ RSignalAddrReg, &SignalAddrReg`
228			`.equ Rpcb, &pcb`
229
230			`.equ Retx, &etx`
231			`.equ Rety, &ety`
232			`.equ Retz, &etz`
233			`.equ Reta, &eta`
234
235			`.equ Retb, &etb`
236			`.equ Retc, &etc`
237			`.equ RTimerExt, &TimerExt`
238			`.equ RTimerUtil, &TimerUtil`
239
240			`.equ RLEDReg, &LEDReg`
241			`.equ RERRReg, &ERRReg`
242
243			`.equ Ret0, &et0`
244			`.equ Ret1, &et1`
245			`.equ Ret2, &et2`
246			`.equ Ret3, &et3`
247
248			`.equ RFPStat0, &FPStat0`
249			`.equ RFPStat1, &FPStat1`
250			`.equ RFPStat2, &FPStat2`
251			`.equ RFPStat3, &FPStat3`
252
253			`.equ Rheapptr, &heapptr`
254			`.equ RHeapPtr, &heapptr`
255			`.equ RArgvPtr, &ArgvPtr`
256
257			`.equ Ret4, &et4`
258			`.equ Ret5, &et5`
259			`.equ Ret6, &et6`
260			`.equ Ret7, &et7`
261
262			`.equ RXLINXReg, &XLINXReg`
263			`.equ RVMBCReg, &VMBCReg`
264			`.equ RUARTReg, &UARTReg`
265			`.equ RETHERReg, ÐERReg`
266
267			`.global RSpillAddrReg, RFillAddrReg, RSignalAddrReg`
268			`.global Rpcb, Retc`
269			`.global RTimerExt, RTimerUtil, RLEDReg, RERRReg`
270			`.global Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb`
271			`.global Retx, Rety, Retz`
272			`.global RFPStat0, RFPStat1, RFPStat2, RFPStat3`
273			`.global Rheapptr, RHeapPtr, RArgvPtr`
274			`.global RXLINXReg, RVMBCReg, RUARTReg, RETHERReg`
275
276			`;`
277			`;*************************************************************************`
278			`;`
279
280
281			`;`
282			`; Rule 3:`
283			`; Gr96-Gr127 Compiler & Programmer use registers.`
284			`; 32 Registers for Compiler & Programmer use`
285
286			`;`
287			`; 16 Registers for Compiler Use.`
288			`;`
289
290			`;`
291			`; Compiler Temporaries and Function Return Values`
292			`;`
293
294			`.reg v0, gr96 ; First word of Return Value`
295			`.reg v1, gr97`
296			`.reg v2, gr98`
297			`.reg v3, gr99`
298
299			`.reg v4, gr100`
300			`.reg v5, gr101`
301			`.reg v6, gr102`
302			`.reg v7, gr103`
303
304			`.reg v8, gr104`
305			`.reg v9, gr105`
306			`.reg v10, gr106`
307			`.reg v11, gr107`
308
309			`.reg v12, gr108`
310			`.reg v13, gr109`
311			`.reg v14, gr110`
312			`.reg v15, gr111`
313
314			`.equ Rv0, &v0`
315			`.equ Rv1, &v1`
316			`.equ Rv2, &v2`
317			`.equ Rv3, &v3`
318
319			`.equ Rv4, &v4`
320			`.equ Rv5, &v5`
321			`.equ Rv6, &v6`
322			`.equ Rv7, &v7`
323
324			`.equ Rv8, &v8`
325			`.equ Rv9, &v9`
326			`.equ Rv10, &v10`
327			`.equ Rv11, &v11`
328
329			`.equ Rv12, &v12`
330			`.equ Rv13, &v13`
331			`.equ Rv14, &v14`
332			`.equ Rv15, &v15`
333
334			`.global Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9`
335			`.global Rv10, Rv11, Rv12, Rv13, Rv14, Rv15`
336
337
338			`;`
339			`; User Process Statics Registers`
340			`;`
341
342			`.reg rp0, gr112 ; Reserved for Programmer, #0`
343			`.reg rp1, gr113 ; Reserved for Programmer, #1`
344			`.reg rp2, gr114 ; Reserved for Programmer, #2`
345			`.reg rp3, gr115 ; Reserved for Programmer, #3`
346
347			`.equ Rrp0, &rp0`
348			`.equ Rrp1, &rp1`
349			`.equ Rrp2, &rp2`
350			`.equ Rrp3, &rp3`
351
352			`.global Rrp0, Rrp1, Rrp2, Rrp3`
353
354			`;`
355			`; Compiler Temporaries II`
356			`;`
357
358			`.reg tv0, gr116 ;`
359			`.reg tv1, gr117 ;`
360			`.reg tv2, gr118 ;`
361			`.reg tv3, gr119 ;`
362			`.reg tv4, gr120 ;`
363
364			`.equ Rtv0, &tv0 ;`
365			`.equ Rtv1, &tv1 ;`
366			`.equ Rtv2, &tv2 ;`
367			`.equ Rtv3, &tv3 ;`
368			`.equ Rtv4, &tv4 ;`
369
370			`.global Rtv0, Rtv1, Rtv2, Rtv3, Rtv4`
371
372			`;`
373			`; Special pointers and registers for handlers and stack operations.`
374			`;`
375
376			`.reg tav, gr121 ; Temp, Arg for Trap Handlers`
377			`.reg tpc, gr122 ; Temp, Ret PC for Trap Handlers`
378			`.reg lrp, gr123 ; Large Return Pointer`
379			`.reg slp, gr124 ; Static Link Pointer`
380
381			`.reg msp, gr125 ; Memory Stack Pointer`
382			`.reg rab, gr126 ; Register Allocate Bound`
383			`.reg rfb, gr127 ; Register Free Bound`
384
385			`.equ Rtav, &tav`
386			`.equ Rtpc, &tpc`
387			`.equ Rlrp, &lrp`
388			`.equ Rslp, &slp`
389			`.equ Rmsp, &msp`
390			`.equ Rrab, &rab`
391			`.equ Rrfb, &rfb`
392
393			`.global Rtav, Rtpc, Rlrp, Rslp, Rmsp, Rrab, Rrfb`