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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [register.ah] - Blame information for rev 173

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; /* @(#)register.ah    1.1 96/05/23 08:56:57, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                naming of various registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  /* $Id: register.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */
 
;* File information and includes.
 
        .file   "register.ah"
        .ident  "@(#)register.ah        1.1 96/05/23 08:56:57, TEI\n"
 
;* Register Stack pointer and frame pointer registers.
 
        .extern Rrsp, Rfp
 
        .reg    regsp,          %%Rrsp
        .reg    fp,             %%Rfp
 
 
        .extern RTrapReg
        .extern Rtrapreg
 
        .reg    TrapReg,        %%RTrapReg
        .reg    trapreg,        %%Rtrapreg
 
 
;* Operating system Interrupt handler registers (gr64-gr67)
 
        .extern ROSint0, ROSint1, ROSint2, ROSint3
 
        .reg    OSint0,         %%ROSint0
        .reg    OSint1,         %%ROSint1
        .reg    OSint2,         %%ROSint2
        .reg    OSint3,         %%ROSint3
 
        .reg    it0,            %%ROSint0
        .reg    it1,            %%ROSint1
        .reg    it2,            %%ROSint2
        .reg    it3,            %%ROSint3
 
 
 
;* Operating system temporary (or scratch) registers (gr68-gr79)
 
        .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3
        .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7
        .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11
 
        .reg    OStmp0,         %%ROStmp0
        .reg    OStmp1,         %%ROStmp1
        .reg    OStmp2,         %%ROStmp2
        .reg    OStmp3,         %%ROStmp3
 
        .reg    OStmp4,         %%ROStmp4
        .reg    OStmp5,         %%ROStmp5
        .reg    OStmp6,         %%ROStmp6
        .reg    OStmp7,         %%ROStmp7
 
        .reg    OStmp8,         %%ROStmp8
        .reg    OStmp9,         %%ROStmp9
        .reg    OStmp10,        %%ROStmp10
        .reg    OStmp11,        %%ROStmp11
 
 
        .reg    kt0,            %%ROStmp0
        .reg    kt1,            %%ROStmp1
        .reg    kt2,            %%ROStmp2
        .reg    kt3,            %%ROStmp3
 
        .reg    kt4,            %%ROStmp4
        .reg    kt5,            %%ROStmp5
        .reg    kt6,            %%ROStmp6
        .reg    kt7,            %%ROStmp7
 
        .reg    kt8,            %%ROStmp8
        .reg    kt9,            %%ROStmp9
        .reg    kt10,           %%ROStmp10
        .reg    kt11,           %%ROStmp11
 
 
        .reg    TempReg0,       %%ROSint0
        .reg    TempReg1,       %%ROSint1
        .reg    TempReg2,       %%ROSint2
        .reg    TempReg3,       %%ROSint3
 
        .reg    TempReg4,       %%ROStmp0
        .reg    TempReg5,       %%ROStmp1
        .reg    TempReg6,       %%ROStmp2
        .reg    TempReg7,       %%ROStmp3
 
        .reg    TempReg8,       %%ROStmp4
        .reg    TempReg9,       %%ROStmp5
        .reg    TempReg10,      %%ROStmp6
        .reg    TempReg11,      %%ROStmp7
 
        .reg    TempReg12,      %%ROStmp8
        .reg    TempReg13,      %%ROStmp9
        .reg    TempReg14,      %%ROStmp10
        .reg    TempReg15,      %%ROStmp11
 
 
;* Assigned static registers
 
        .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg
        .extern Rpcb, Retc
        .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg
        .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb
        .extern Retx, Rety, Retz
 
 
        .reg    SpillAddrReg,   %%RSpillAddrReg
        .reg    FillAddrReg,    %%RFillAddrReg
        .reg    SignalAddrReg,  %%RSignalAddrReg
        .reg    pcb,            %%Rpcb
 
        .reg    etx,            %%Retx
        .reg    ety,            %%Rety
        .reg    etz,            %%Retz
        .reg    eta,            %%Reta
 
        .reg    etb,            %%Retb
        .reg    etc,            %%Retc
        .reg    TimerExt,       %%RTimerExt
        .reg    TimerUtil,      %%RTimerUtil
 
        .reg    LEDReg,         %%RLEDReg
        .reg    ERRReg,         %%RERRReg
 
 
        .reg    et0,            %%Ret0
        .reg    et1,            %%Ret1
        .reg    et2,            %%Ret2
        .reg    et3,            %%Ret3
 
        .reg    et4,            %%Ret4
        .reg    et5,            %%Ret5
        .reg    et6,            %%Ret6
        .reg    et7,            %%Ret7
 
;
        .equ    SCB1REG_NUM,    88
        .reg    SCB1REG_PTR,    %%Ret0
 
; The floating point trap handlers need a few static registers
 
        .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3
        .extern Rheapptr, RHeapPtr, RArgvPtr
 
        .reg    FPStat0,        %%RFPStat0
        .reg    FPStat1,        %%RFPStat1
        .reg    FPStat2,        %%RFPStat2
        .reg    FPStat3,        %%RFPStat3
 
        .reg    heapptr,        %%Rheapptr
        .reg    HeapPtr,        %%RHeapPtr
        .reg    ArgvPtr,        %%RArgvPtr
 
        .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg
 
        .reg    XLINXReg,       %%RXLINXReg
        .reg    VMBCReg,        %%RVMBCReg
        .reg    UARTReg,        %%RUARTReg
        .reg    ETHERReg,       %%RXLINXReg
 
;* Compiler and programmer registers. (gr96-gr127)
 
        .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9
        .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15
 
        .reg    v0,             %%Rv0
        .reg    v1,             %%Rv1
        .reg    v2,             %%Rv2
        .reg    v3,             %%Rv3
 
        .reg    v4,             %%Rv4
        .reg    v5,             %%Rv5
        .reg    v6,             %%Rv6
        .reg    v7,             %%Rv7
 
        .reg    v8,             %%Rv8
        .reg    v9,             %%Rv9
        .reg    v10,            %%Rv10
        .reg    v11,            %%Rv11
 
        .reg    v12,            %%Rv12
        .reg    v13,            %%Rv13
        .reg    v14,            %%Rv14
        .reg    v15,            %%Rv15
 
        .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4
 
        .reg    tv0,            %%Rtv0
        .reg    tv1,            %%Rtv1
        .reg    tv2,            %%Rtv2
        .reg    tv3,            %%Rtv3
        .reg    tv4,            %%Rtv4
 
; ****************************************************************************
;       For uatrap
; register definitions -- since this trap handler must allow for
; nested traps and interrupts such as TLB miss, protection violation,
; or Data Access Exception, and these trap handlers use the shared
; Temp registers, we must maintain our own that are safe over user-
; mode loads and stores.  The following must be assigned global
; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss,
; TLB protection violation, or data exception trap handlers.
 
;       .reg    cha_cpy,        OStmp4          ; copy of CHA
;       .reg    chd_cpy,        OStmp5          ; copy of CHD
;       .reg    chc_cpy,        OStmp6          ; copy of CHC
;       .reg    LTemp0,         OStmp7          ; local temp 0
;       .reg    LTemp1,         OStmp8          ; local temp 1
 
; ****************************************************************************

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [start/] [register.ah] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */`
2			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
3			`; naming of various registers`
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; /* $Id: register.ah,v 1.2 2001-09-27 11:59:42 chris Exp $ */`
6
7			`;* File information and includes.`
8
9			`.file "register.ah"`
10			`.ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n"`
11
12			`;* Register Stack pointer and frame pointer registers.`
13
14			`.extern Rrsp, Rfp`
15
16			`.reg regsp, %%Rrsp`
17			`.reg fp, %%Rfp`
18
19
20			`.extern RTrapReg`
21			`.extern Rtrapreg`
22
23			`.reg TrapReg, %%RTrapReg`
24			`.reg trapreg, %%Rtrapreg`
25
26
27			`;* Operating system Interrupt handler registers (gr64-gr67)`
28
29			`.extern ROSint0, ROSint1, ROSint2, ROSint3`
30
31			`.reg OSint0, %%ROSint0`
32			`.reg OSint1, %%ROSint1`
33			`.reg OSint2, %%ROSint2`
34			`.reg OSint3, %%ROSint3`
35
36			`.reg it0, %%ROSint0`
37			`.reg it1, %%ROSint1`
38			`.reg it2, %%ROSint2`
39			`.reg it3, %%ROSint3`
40
41
42
43			`;* Operating system temporary (or scratch) registers (gr68-gr79)`
44
45			`.extern ROStmp0, ROStmp1, ROStmp2, ROStmp3`
46			`.extern ROStmp4, ROStmp5, ROStmp6, ROStmp7`
47			`.extern ROStmp8, ROStmp9, ROStmp10, ROStmp11`
48
49			`.reg OStmp0, %%ROStmp0`
50			`.reg OStmp1, %%ROStmp1`
51			`.reg OStmp2, %%ROStmp2`
52			`.reg OStmp3, %%ROStmp3`
53
54			`.reg OStmp4, %%ROStmp4`
55			`.reg OStmp5, %%ROStmp5`
56			`.reg OStmp6, %%ROStmp6`
57			`.reg OStmp7, %%ROStmp7`
58
59			`.reg OStmp8, %%ROStmp8`
60			`.reg OStmp9, %%ROStmp9`
61			`.reg OStmp10, %%ROStmp10`
62			`.reg OStmp11, %%ROStmp11`
63
64
65			`.reg kt0, %%ROStmp0`
66			`.reg kt1, %%ROStmp1`
67			`.reg kt2, %%ROStmp2`
68			`.reg kt3, %%ROStmp3`
69
70			`.reg kt4, %%ROStmp4`
71			`.reg kt5, %%ROStmp5`
72			`.reg kt6, %%ROStmp6`
73			`.reg kt7, %%ROStmp7`
74
75			`.reg kt8, %%ROStmp8`
76			`.reg kt9, %%ROStmp9`
77			`.reg kt10, %%ROStmp10`
78			`.reg kt11, %%ROStmp11`
79
80
81			`.reg TempReg0, %%ROSint0`
82			`.reg TempReg1, %%ROSint1`
83			`.reg TempReg2, %%ROSint2`
84			`.reg TempReg3, %%ROSint3`
85
86			`.reg TempReg4, %%ROStmp0`
87			`.reg TempReg5, %%ROStmp1`
88			`.reg TempReg6, %%ROStmp2`
89			`.reg TempReg7, %%ROStmp3`
90
91			`.reg TempReg8, %%ROStmp4`
92			`.reg TempReg9, %%ROStmp5`
93			`.reg TempReg10, %%ROStmp6`
94			`.reg TempReg11, %%ROStmp7`
95
96			`.reg TempReg12, %%ROStmp8`
97			`.reg TempReg13, %%ROStmp9`
98			`.reg TempReg14, %%ROStmp10`
99			`.reg TempReg15, %%ROStmp11`
100
101
102			`;* Assigned static registers`
103
104			`.extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg`
105			`.extern Rpcb, Retc`
106			`.extern RTimerExt, RTimerUtil, RLEDReg, RERRReg`
107			`.extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb`
108			`.extern Retx, Rety, Retz`
109
110
111			`.reg SpillAddrReg, %%RSpillAddrReg`
112			`.reg FillAddrReg, %%RFillAddrReg`
113			`.reg SignalAddrReg, %%RSignalAddrReg`
114			`.reg pcb, %%Rpcb`
115
116			`.reg etx, %%Retx`
117			`.reg ety, %%Rety`
118			`.reg etz, %%Retz`
119			`.reg eta, %%Reta`
120
121			`.reg etb, %%Retb`
122			`.reg etc, %%Retc`
123			`.reg TimerExt, %%RTimerExt`
124			`.reg TimerUtil, %%RTimerUtil`
125
126			`.reg LEDReg, %%RLEDReg`
127			`.reg ERRReg, %%RERRReg`
128
129
130			`.reg et0, %%Ret0`
131			`.reg et1, %%Ret1`
132			`.reg et2, %%Ret2`
133			`.reg et3, %%Ret3`
134
135			`.reg et4, %%Ret4`
136			`.reg et5, %%Ret5`
137			`.reg et6, %%Ret6`
138			`.reg et7, %%Ret7`
139
140			`;`
141			`.equ SCB1REG_NUM, 88`
142			`.reg SCB1REG_PTR, %%Ret0`
143
144			`; The floating point trap handlers need a few static registers`
145
146			`.extern RFPStat0, RFPStat1, RFPStat2, RFPStat3`
147			`.extern Rheapptr, RHeapPtr, RArgvPtr`
148
149			`.reg FPStat0, %%RFPStat0`
150			`.reg FPStat1, %%RFPStat1`
151			`.reg FPStat2, %%RFPStat2`
152			`.reg FPStat3, %%RFPStat3`
153
154			`.reg heapptr, %%Rheapptr`
155			`.reg HeapPtr, %%RHeapPtr`
156			`.reg ArgvPtr, %%RArgvPtr`
157
158			`.extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg`
159
160			`.reg XLINXReg, %%RXLINXReg`
161			`.reg VMBCReg, %%RVMBCReg`
162			`.reg UARTReg, %%RUARTReg`
163			`.reg ETHERReg, %%RXLINXReg`
164
165			`;* Compiler and programmer registers. (gr96-gr127)`
166
167			`.extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9`
168			`.extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15`
169
170			`.reg v0, %%Rv0`
171			`.reg v1, %%Rv1`
172			`.reg v2, %%Rv2`
173			`.reg v3, %%Rv3`
174
175			`.reg v4, %%Rv4`
176			`.reg v5, %%Rv5`
177			`.reg v6, %%Rv6`
178			`.reg v7, %%Rv7`
179
180			`.reg v8, %%Rv8`
181			`.reg v9, %%Rv9`
182			`.reg v10, %%Rv10`
183			`.reg v11, %%Rv11`
184
185			`.reg v12, %%Rv12`
186			`.reg v13, %%Rv13`
187			`.reg v14, %%Rv14`
188			`.reg v15, %%Rv15`
189
190			`.extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4`
191
192			`.reg tv0, %%Rtv0`
193			`.reg tv1, %%Rtv1`
194			`.reg tv2, %%Rtv2`
195			`.reg tv3, %%Rtv3`
196			`.reg tv4, %%Rtv4`
197
198			`; ****************************************************************************`
199			`; For uatrap`
200			`; register definitions -- since this trap handler must allow for`
201			`; nested traps and interrupts such as TLB miss, protection violation,`
202			`; or Data Access Exception, and these trap handlers use the shared`
203			`; Temp registers, we must maintain our own that are safe over user-`
204			`; mode loads and stores. The following must be assigned global`
205			`; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss,`
206			`; TLB protection violation, or data exception trap handlers.`
207
208			`; .reg cha_cpy, OStmp4 ; copy of CHA`
209			`; .reg chd_cpy, OStmp5 ; copy of CHD`
210			`; .reg chc_cpy, OStmp6 ; copy of CHC`
211			`; .reg LTemp0, OStmp7 ; local temp 0`
212			`; .reg LTemp1, OStmp8 ; local temp 1`
213
214			`; ****************************************************************************`