OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [a29k/] [portsw/] [startup/] [setvec.c] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  set_vector
2
 *
3
 *  This routine installs an interrupt vector on the target Board/CPU.
4
 *  This routine is allowed to be as board dependent as necessary.
5
 *
6
 *  INPUT:
7
 *    handler - interrupt handler entry point
8
 *    vector  - vector number
9
 *    type    - 0 indicates raw hardware connect
10
 *              1 indicates RTEMS interrupt connect
11
 *
12
 *  RETURNS:
13
 *    address of previous interrupt handler
14
 *
15
 *  COPYRIGHT (c) 1989-1999.
16
 *  On-Line Applications Research Corporation (OAR).
17
 *
18
 *  The license and distribution terms for this file may be
19
 *  found in the file LICENSE in this distribution or at
20
 *  http://www.OARcorp.com/rtems/license.html.
21
 *
22
 *  $Id: setvec.c,v 1.2 2001-09-27 11:59:42 chris Exp $
23
 */
24
 
25
#include <rtems.h>
26
#include <bsp.h>
27
 
28
#ifndef lint
29
static char _sccsid[] = "@(#)setvec.c 06/30/96     1.2\n";
30
#endif
31
 
32
no_cpu_isr_entry set_vector(                    /* returns old vector */
33
  rtems_isr_entry     handler,                  /* isr routine        */
34
  rtems_vector_number vector,                   /* vector number      */
35
  int                 type                      /* RTEMS or RAW intr  */
36
)
37
{
38
  no_cpu_isr_entry previous_isr;
39
 
40
  if ( type )
41
    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
42
  else {
43
    /* XXX: install non-RTEMS ISR as "raw" interupt */
44
    _settrap( vector, handler );
45
  }
46
  return previous_isr;
47
}
48
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.