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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i386/] [pc386/] [3c509/] [3c509.h] - Blame information for rev 173

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/*
2
 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
3
 *
4
 * Redistribution and use in source and binary forms, with or without
5
 * modification, are permitted provided that the following conditions are
6
 * met: 1. Redistributions of source code must retain the above copyright
7
 * notice, this list of conditions and the following disclaimer. 2. The name
8
 * of the author may not be used to endorse or promote products derived from
9
 * this software without specific prior written permission
10
 *
11
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14
 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21
 *
22
 * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
23
 *
24
 October 2, 1994
25
 
26
 Modified by: Andres Vega Garcia
27
 
28
 INRIA - Sophia Antipolis, France
29
 e-mail: avega@sophia.inria.fr
30
 finger: avega@pax.inria.fr
31
 
32
 */
33
/*
34
 *  $Id: 3c509.h,v 1.2 2001-09-27 11:59:47 chris Exp $
35
 *
36
 *  Promiscuous mode added and interrupt logic slightly changed
37
 *  to reduce the number of adapter failures. Transceiver select
38
 *  logic changed to use value from EEPROM. Autoconfiguration
39
 *  features added.
40
 *  Done by:
41
 *          Serge Babkin
42
 *          Chelindbank (Chelyabinsk, Russia)
43
 *          babkin@hq.icb.chel.su
44
 */
45
 
46
/*
47
 * Pccard support for 3C589 by:
48
 *              HAMADA Naoki
49
 *              nao@tom-yam.or.jp
50
 */
51
 
52
/*
53
typedef unsigned short u_short;
54
typedef unsigned long  u_long;
55
typedef unsigned char  u_char;
56
*/
57
 
58
/*
59
 * Some global constants
60
 */
61
#define         F_RX_FIRST       0x1
62
#define         F_PROMISC        0x8
63
#define         F_ACCESS_32_BITS 0x100
64
 
65
#define TX_INIT_RATE         16
66
#define TX_INIT_MAX_RATE     64
67
#define RX_INIT_LATENCY      64
68
#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
69
#define RX_NEXT_EARLY_THRESH 500
70
 
71
#define EEPROMSIZE      0x40
72
#define MAX_EEPROMBUSY  1000
73
#define EP_LAST_TAG     0xd7
74
#define EP_MAX_BOARDS   16
75
/*
76
 * This `ID' port is a mere hack.  There's currently no chance to register
77
 * it with config's idea of the ports that are in use.
78
 *
79
 * "After the automatic configuration is completed, the IDS is in its initial
80
 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
81
 * 'x' is any hex digit.  If a zero is written to any one of these ports, then
82
 * that address is remembered and becomes the ID port.  A second zero written
83
 * to that port resets the ID sequence to its initial state.  The IDS watches
84
 * for the ID sequence to be written to the ID port."
85
 *
86
 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
87
 * ports.
88
 */
89
#define EP_ID_PORT      0x110
90
#define EP_IOSIZE       16      /* 16 bytes of I/O space used. */
91
 
92
/*
93
 * some macros to acces long named fields
94
 */
95
#define IS_BASE (is->id_iobase)
96
#define BASE    (sc->ep_io_addr)
97
 
98
/*
99
 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
100
 * Offset 0xa)
101
 */
102
#define EEPROM_CMD_RD    0x0080 /* Read:  Address required (5 bits) */
103
#define EEPROM_CMD_WR    0x0040 /* Write: Address required (5 bits) */
104
#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
105
#define EEPROM_CMD_EWEN  0x0030 /* Erase/Write Enable: No data required */
106
 
107
#define EEPROM_BUSY             (1<<15)
108
#define EEPROM_TST_MODE         (1<<14)
109
 
110
/*
111
 * Some short functions, worth to let them be a macro
112
 */
113
#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
114
#define GO_WINDOW(x)      outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
115
 
116
/**************************************************************************
117
 *                                                                        *
118
 * These define the EEPROM data structure.  They are used in the probe
119
 * function to verify the existence of the adapter after having sent
120
 * the ID_Sequence.
121
 *
122
 * There are others but only the ones we use are defined here.
123
 *
124
 **************************************************************************/
125
 
126
#define EEPROM_NODE_ADDR_0      0x0     /* Word */
127
#define EEPROM_NODE_ADDR_1      0x1     /* Word */
128
#define EEPROM_NODE_ADDR_2      0x2     /* Word */
129
#define EEPROM_PROD_ID          0x3     /* 0x9[0-f]50 */
130
#define EEPROM_MFG_ID           0x7     /* 0x6d50 */
131
#define EEPROM_ADDR_CFG         0x8     /* Base addr */
132
#define EEPROM_RESOURCE_CFG     0x9     /* IRQ. Bits 12-15 */
133
 
134
/**************************************************************************
135
 *                                                                                *
136
 * These are the registers for the 3Com 3c509 and their bit patterns when *
137
 * applicable.  They have been taken out the the "EtherLink III Parallel  *
138
 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
139
 * from 3com.                                                             *
140
 *                                                                                *
141
 **************************************************************************/
142
 
143
#define EP_COMMAND              0x0e    /* Write. BASE+0x0e is always a
144
                                         * command reg. */
145
#define EP_STATUS               0x0e    /* Read. BASE+0x0e is always status
146
                                         * reg. */
147
#define EP_WINDOW               0x0f    /* Read. BASE+0x0f is always window
148
                                         * reg. */
149
/*
150
 * Window 0 registers. Setup.
151
 */
152
/* Write */
153
#define EP_W0_EEPROM_DATA       0x0c
154
#define EP_W0_EEPROM_COMMAND    0x0a
155
#define EP_W0_RESOURCE_CFG      0x08
156
#define EP_W0_ADDRESS_CFG       0x06
157
#define EP_W0_CONFIG_CTRL       0x04
158
/* Read */
159
#define EP_W0_PRODUCT_ID        0x02
160
#define EP_W0_MFG_ID            0x00
161
 
162
/*
163
 * Window 1 registers. Operating Set.
164
 */
165
/* Write */
166
#define EP_W1_TX_PIO_WR_2       0x02
167
#define EP_W1_TX_PIO_WR_1       0x00
168
/* Read */
169
#define EP_W1_FREE_TX           0x0c
170
#define EP_W1_TX_STATUS         0x0b    /* byte */
171
#define EP_W1_TIMER             0x0a    /* byte */
172
#define EP_W1_RX_STATUS         0x08
173
#define EP_W1_RX_PIO_RD_2       0x02
174
#define EP_W1_RX_PIO_RD_1       0x00
175
 
176
/*
177
 * Window 2 registers. Station Address Setup/Read
178
 */
179
/* Read/Write */
180
#define EP_W2_ADDR_5            0x05
181
#define EP_W2_ADDR_4            0x04
182
#define EP_W2_ADDR_3            0x03
183
#define EP_W2_ADDR_2            0x02
184
#define EP_W2_ADDR_1            0x01
185
#define EP_W2_ADDR_0            0x00
186
 
187
/*
188
 * Window 3 registers.  FIFO Management.
189
 */
190
/* Read */
191
#define EP_W3_FREE_TX           0x0c
192
#define EP_W3_FREE_RX           0x0a
193
 
194
/*
195
 * Window 4 registers. Diagnostics.
196
 */
197
/* Read/Write */
198
#define EP_W4_MEDIA_TYPE        0x0a
199
#define EP_W4_CTRLR_STATUS      0x08
200
#define EP_W4_NET_DIAG          0x06
201
#define EP_W4_FIFO_DIAG         0x04
202
#define EP_W4_HOST_DIAG         0x02
203
#define EP_W4_TX_DIAG           0x00
204
 
205
/*
206
 * Window 5 Registers.  Results and Internal status.
207
 */
208
/* Read */
209
#define EP_W5_READ_0_MASK       0x0c
210
#define EP_W5_INTR_MASK         0x0a
211
#define EP_W5_RX_FILTER         0x08
212
#define EP_W5_RX_EARLY_THRESH   0x06
213
#define EP_W5_TX_AVAIL_THRESH   0x02
214
#define EP_W5_TX_START_THRESH   0x00
215
 
216
/*
217
 * Window 6 registers. Statistics.
218
 */
219
/* Read/Write */
220
#define TX_TOTAL_OK             0x0c
221
#define RX_TOTAL_OK             0x0a
222
#define TX_DEFERRALS            0x08
223
#define RX_FRAMES_OK            0x07
224
#define TX_FRAMES_OK            0x06
225
#define RX_OVERRUNS             0x05
226
#define TX_COLLISIONS           0x04
227
#define TX_AFTER_1_COLLISION    0x03
228
#define TX_AFTER_X_COLLISIONS   0x02
229
#define TX_NO_SQE               0x01
230
#define TX_CD_LOST              0x00
231
 
232
/****************************************
233
 *
234
 * Register definitions.
235
 *
236
 ****************************************/
237
 
238
/*
239
 * Command register. All windows.
240
 *
241
 * 16 bit register.
242
 *     15-11:  5-bit code for command to be executed.
243
 *     10-0:   11-bit arg if any. For commands with no args;
244
 *            this can be set to anything.
245
 */
246
#define GLOBAL_RESET            (u_short) 0x0000        /* Wait at least 1ms
247
                                                         * after issuing */
248
#define WINDOW_SELECT           (u_short) (0x1<<11)
249
#define START_TRANSCEIVER       (u_short) (0x2<<11)     /* Read ADDR_CFG reg to
250
                                                         * determine whether
251
                                                         * this is needed. If
252
                                                         * so; wait 800 uSec
253
                                                         * before using trans-
254
                                                         * ceiver. */
255
#define RX_DISABLE              (u_short) (0x3<<11)     /* state disabled on
256
                                                         * power-up */
257
#define RX_ENABLE               (u_short) (0x4<<11)
258
#define RX_RESET                (u_short) (0x5<<11)
259
#define RX_DISCARD_TOP_PACK     (u_short) (0x8<<11)
260
#define TX_ENABLE               (u_short) (0x9<<11)
261
#define TX_DISABLE              (u_short) (0xa<<11)
262
#define TX_RESET                (u_short) (0xb<<11)
263
#define REQ_INTR                (u_short) (0xc<<11)
264
#define SET_INTR_MASK           (u_short) (0xe<<11)
265
#define SET_RD_0_MASK           (u_short) (0xf<<11)
266
#define SET_RX_FILTER           (u_short) (0x10<<11)
267
#define FIL_INDIVIDUAL  (u_short) (0x1)
268
#define FIL_GROUP               (u_short) (0x2)
269
#define FIL_BRDCST      (u_short) (0x4)
270
#define FIL_ALL         (u_short) (0x8)
271
#define SET_RX_EARLY_THRESH     (u_short) (0x11<<11)
272
#define SET_TX_AVAIL_THRESH     (u_short) (0x12<<11)
273
#define SET_TX_START_THRESH     (u_short) (0x13<<11)
274
#define STATS_ENABLE            (u_short) (0x15<<11)
275
#define STATS_DISABLE           (u_short) (0x16<<11)
276
#define STOP_TRANSCEIVER        (u_short) (0x17<<11)
277
/*
278
 * The following C_* acknowledge the various interrupts. Some of them don't
279
 * do anything.  See the manual.
280
 */
281
#define ACK_INTR                (u_short) (0x6800)
282
#define C_INTR_LATCH    (u_short) (ACK_INTR|0x1)
283
#define C_CARD_FAILURE  (u_short) (ACK_INTR|0x2)
284
#define C_TX_COMPLETE   (u_short) (ACK_INTR|0x4)
285
#define C_TX_AVAIL      (u_short) (ACK_INTR|0x8)
286
#define C_RX_COMPLETE   (u_short) (ACK_INTR|0x10)
287
#define C_RX_EARLY      (u_short) (ACK_INTR|0x20)
288
#define C_INT_RQD               (u_short) (ACK_INTR|0x40)
289
#define C_UPD_STATS     (u_short) (ACK_INTR|0x80)
290
#define C_MASK  (u_short) 0xFF /* mask of C_* */
291
 
292
/*
293
 * Status register. All windows.
294
 *
295
 *     15-13:  Window number(0-7).
296
 *     12:     Command_in_progress.
297
 *     11:     reserved.
298
 *     10:     reserved.
299
 *     9:      reserved.
300
 *     8:      reserved.
301
 *     7:      Update Statistics.
302
 *     6:      Interrupt Requested.
303
 *     5:      RX Early.
304
 *     4:      RX Complete.
305
 *     3:      TX Available.
306
 *     2:      TX Complete.
307
 *     1:      Adapter Failure.
308
 *     0:      Interrupt Latch.
309
 */
310
#define S_INTR_LATCH            (u_short) (0x1)
311
#define S_CARD_FAILURE          (u_short) (0x2)
312
#define S_TX_COMPLETE           (u_short) (0x4)
313
#define S_TX_AVAIL              (u_short) (0x8)
314
#define S_RX_COMPLETE           (u_short) (0x10)
315
#define S_RX_EARLY              (u_short) (0x20)
316
#define S_INT_RQD               (u_short) (0x40)
317
#define S_UPD_STATS             (u_short) (0x80)
318
#define S_MASK  (u_short) 0xFF /* mask of S_* */
319
#define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
320
                                 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
321
#define S_COMMAND_IN_PROGRESS   (u_short) (0x1000)
322
 
323
/* Address Config. Register.
324
 * Window 0/Port 06
325
 */
326
 
327
#define ACF_CONNECTOR_BITS      14
328
#define ACF_CONNECTOR_UTP       0
329
#define ACF_CONNECTOR_AUI       1
330
#define ACF_CONNECTOR_BNC       3
331
 
332
/* Resource configuration register.
333
 * Window 0/Port 08
334
 *
335
 */
336
 
337
#define SET_IRQ(base,irq)     outw((base) + EP_W0_RESOURCE_CFG, \
338
                              ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
339
                              ((u_short)(irq)<<12))  ) /* set IRQ i */
340
 
341
/*
342
 * FIFO Registers.
343
 * RX Status. Window 1/Port 08
344
 *
345
 *     15:     Incomplete or FIFO empty.
346
 *     14:     1: Error in RX Packet   0: Incomplete or no error.
347
 *     13-11:  Type of error.
348
 *            1000 = Overrun.
349
 *            1011 = Run Packet Error.
350
 *            1100 = Alignment Error.
351
 *            1101 = CRC Error.
352
 *            1001 = Oversize Packet Error (>1514 bytes)
353
 *            0010 = Dribble Bits.
354
 *            (all other error codes, no errors.)
355
 *
356
 *     10-0:   RX Bytes (0-1514)
357
 */
358
#define ERR_RX_INCOMPLETE  (u_short) (0x1<<15)
359
#define ERR_RX             (u_short) (0x1<<14)
360
#define ERR_RX_OVERRUN     (u_short) (0x8<<11)
361
#define ERR_RX_RUN_PKT     (u_short) (0xb<<11)
362
#define ERR_RX_ALIGN       (u_short) (0xc<<11)
363
#define ERR_RX_CRC         (u_short) (0xd<<11)
364
#define ERR_RX_OVERSIZE    (u_short) (0x9<<11)
365
#define ERR_RX_DRIBBLE     (u_short) (0x2<<11)
366
 
367
/*
368
 * FIFO Registers.
369
 * TX Status. Window 1/Port 0B
370
 *
371
 *   Reports the transmit status of a completed transmission. Writing this
372
 *   register pops the transmit completion stack.
373
 *
374
 *   Window 1/Port 0x0b.
375
 *
376
 *     7:      Complete
377
 *     6:      Interrupt on successful transmission requested.
378
 *     5:      Jabber Error (TP Only, TX Reset required. )
379
 *     4:      Underrun (TX Reset required. )
380
 *     3:      Maximum Collisions.
381
 *     2:      TX Status Overflow.
382
 *     1-0:    Undefined.
383
 *
384
 */
385
#define TXS_COMPLETE            0x80
386
#define TXS_SUCCES_INTR_REQ             0x40
387
#define TXS_JABBER              0x20
388
#define TXS_UNDERRUN            0x10
389
#define TXS_MAX_COLLISION       0x8
390
#define TXS_STATUS_OVERFLOW     0x4
391
 
392
/*
393
 * Configuration control register.
394
 * Window 0/Port 04
395
 */
396
/* Read */
397
#define IS_AUI                          (1<<13)
398
#define IS_BNC                          (1<<12)
399
#define IS_UTP                          (1<<9)
400
/* Write */
401
#define ENABLE_DRQ_IRQ                  0x0001
402
#define W0_P4_CMD_RESET_ADAPTER       0x4
403
#define W0_P4_CMD_ENABLE_ADAPTER      0x1
404
/*
405
 * Media type and status.
406
 * Window 4/Port 0A
407
 */
408
#define ENABLE_UTP                      0xc0
409
#define DISABLE_UTP                     0x0
410
 
411
/*
412
 * Misc defines for various things.
413
 */
414
#define ACTIVATE_ADAPTER_TO_CONFIG      0xff /* to the id_port */
415
#define MFG_ID                          0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
416
#define PROD_ID                         0x9150
417
 
418
#define AUI                             0x1
419
#define BNC                             0x2
420
#define UTP                             0x4
421
 
422
#define RX_BYTES_MASK                   (u_short) (0x07ff)
423
 

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