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/*
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* Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer. 2. The name
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* of the author may not be used to endorse or promote products derived from
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* this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
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*
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October 2, 1994
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Modified by: Andres Vega Garcia
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INRIA - Sophia Antipolis, France
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e-mail: avega@sophia.inria.fr
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finger: avega@pax.inria.fr
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*/
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/*
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* $Id: 3c509.h,v 1.2 2001-09-27 11:59:47 chris Exp $
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*
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* Promiscuous mode added and interrupt logic slightly changed
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* to reduce the number of adapter failures. Transceiver select
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* logic changed to use value from EEPROM. Autoconfiguration
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* features added.
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* Done by:
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* Serge Babkin
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* Chelindbank (Chelyabinsk, Russia)
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* babkin@hq.icb.chel.su
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*/
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/*
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* Pccard support for 3C589 by:
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* HAMADA Naoki
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* nao@tom-yam.or.jp
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*/
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/*
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typedef unsigned short u_short;
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typedef unsigned long u_long;
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typedef unsigned char u_char;
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*/
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/*
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* Some global constants
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*/
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#define F_RX_FIRST 0x1
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#define F_PROMISC 0x8
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#define F_ACCESS_32_BITS 0x100
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#define TX_INIT_RATE 16
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#define TX_INIT_MAX_RATE 64
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#define RX_INIT_LATENCY 64
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#define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
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#define RX_NEXT_EARLY_THRESH 500
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#define EEPROMSIZE 0x40
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#define MAX_EEPROMBUSY 1000
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#define EP_LAST_TAG 0xd7
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#define EP_MAX_BOARDS 16
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/*
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* This `ID' port is a mere hack. There's currently no chance to register
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* it with config's idea of the ports that are in use.
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*
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* "After the automatic configuration is completed, the IDS is in its initial
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* state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
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* 'x' is any hex digit. If a zero is written to any one of these ports, then
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* that address is remembered and becomes the ID port. A second zero written
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* to that port resets the ID sequence to its initial state. The IDS watches
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* for the ID sequence to be written to the ID port."
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*
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* We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
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* ports.
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*/
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#define EP_ID_PORT 0x110
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#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */
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/*
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* some macros to acces long named fields
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*/
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#define IS_BASE (is->id_iobase)
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#define BASE (sc->ep_io_addr)
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/*
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* Commands to read/write EEPROM trough EEPROM command register (Window 0,
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* Offset 0xa)
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*/
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#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
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#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
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#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
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#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
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#define EEPROM_BUSY (1<<15)
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#define EEPROM_TST_MODE (1<<14)
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/*
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* Some short functions, worth to let them be a macro
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*/
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#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
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#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
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/**************************************************************************
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* *
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* These define the EEPROM data structure. They are used in the probe
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* function to verify the existence of the adapter after having sent
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* the ID_Sequence.
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*
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* There are others but only the ones we use are defined here.
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*
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**************************************************************************/
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#define EEPROM_NODE_ADDR_0 0x0 /* Word */
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#define EEPROM_NODE_ADDR_1 0x1 /* Word */
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#define EEPROM_NODE_ADDR_2 0x2 /* Word */
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#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
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#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
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#define EEPROM_ADDR_CFG 0x8 /* Base addr */
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#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
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/**************************************************************************
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* *
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* These are the registers for the 3Com 3c509 and their bit patterns when *
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* applicable. They have been taken out the the "EtherLink III Parallel *
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* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
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* from 3com. *
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* *
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**************************************************************************/
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#define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
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* command reg. */
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#define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
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* reg. */
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#define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
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* reg. */
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/*
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* Window 0 registers. Setup.
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*/
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/* Write */
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#define EP_W0_EEPROM_DATA 0x0c
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#define EP_W0_EEPROM_COMMAND 0x0a
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#define EP_W0_RESOURCE_CFG 0x08
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#define EP_W0_ADDRESS_CFG 0x06
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#define EP_W0_CONFIG_CTRL 0x04
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/* Read */
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#define EP_W0_PRODUCT_ID 0x02
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#define EP_W0_MFG_ID 0x00
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/*
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* Window 1 registers. Operating Set.
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*/
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/* Write */
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#define EP_W1_TX_PIO_WR_2 0x02
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#define EP_W1_TX_PIO_WR_1 0x00
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/* Read */
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#define EP_W1_FREE_TX 0x0c
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#define EP_W1_TX_STATUS 0x0b /* byte */
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#define EP_W1_TIMER 0x0a /* byte */
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#define EP_W1_RX_STATUS 0x08
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#define EP_W1_RX_PIO_RD_2 0x02
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#define EP_W1_RX_PIO_RD_1 0x00
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/*
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* Window 2 registers. Station Address Setup/Read
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*/
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/* Read/Write */
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#define EP_W2_ADDR_5 0x05
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#define EP_W2_ADDR_4 0x04
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#define EP_W2_ADDR_3 0x03
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#define EP_W2_ADDR_2 0x02
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#define EP_W2_ADDR_1 0x01
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#define EP_W2_ADDR_0 0x00
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/*
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* Window 3 registers. FIFO Management.
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*/
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/* Read */
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#define EP_W3_FREE_TX 0x0c
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#define EP_W3_FREE_RX 0x0a
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/*
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* Window 4 registers. Diagnostics.
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*/
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/* Read/Write */
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#define EP_W4_MEDIA_TYPE 0x0a
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#define EP_W4_CTRLR_STATUS 0x08
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#define EP_W4_NET_DIAG 0x06
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#define EP_W4_FIFO_DIAG 0x04
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#define EP_W4_HOST_DIAG 0x02
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#define EP_W4_TX_DIAG 0x00
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/*
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* Window 5 Registers. Results and Internal status.
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*/
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/* Read */
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#define EP_W5_READ_0_MASK 0x0c
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#define EP_W5_INTR_MASK 0x0a
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#define EP_W5_RX_FILTER 0x08
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#define EP_W5_RX_EARLY_THRESH 0x06
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#define EP_W5_TX_AVAIL_THRESH 0x02
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#define EP_W5_TX_START_THRESH 0x00
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/*
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* Window 6 registers. Statistics.
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*/
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/* Read/Write */
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#define TX_TOTAL_OK 0x0c
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#define RX_TOTAL_OK 0x0a
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#define TX_DEFERRALS 0x08
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#define RX_FRAMES_OK 0x07
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#define TX_FRAMES_OK 0x06
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#define RX_OVERRUNS 0x05
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#define TX_COLLISIONS 0x04
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#define TX_AFTER_1_COLLISION 0x03
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#define TX_AFTER_X_COLLISIONS 0x02
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#define TX_NO_SQE 0x01
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#define TX_CD_LOST 0x00
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/****************************************
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*
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* Register definitions.
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*
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****************************************/
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/*
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* Command register. All windows.
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*
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* 16 bit register.
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* 15-11: 5-bit code for command to be executed.
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* 10-0: 11-bit arg if any. For commands with no args;
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* this can be set to anything.
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*/
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#define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
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* after issuing */
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#define WINDOW_SELECT (u_short) (0x1<<11)
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#define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
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* determine whether
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* this is needed. If
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* so; wait 800 uSec
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* before using trans-
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* ceiver. */
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#define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
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* power-up */
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#define RX_ENABLE (u_short) (0x4<<11)
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#define RX_RESET (u_short) (0x5<<11)
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#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
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#define TX_ENABLE (u_short) (0x9<<11)
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#define TX_DISABLE (u_short) (0xa<<11)
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#define TX_RESET (u_short) (0xb<<11)
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#define REQ_INTR (u_short) (0xc<<11)
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#define SET_INTR_MASK (u_short) (0xe<<11)
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#define SET_RD_0_MASK (u_short) (0xf<<11)
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#define SET_RX_FILTER (u_short) (0x10<<11)
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#define FIL_INDIVIDUAL (u_short) (0x1)
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#define FIL_GROUP (u_short) (0x2)
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#define FIL_BRDCST (u_short) (0x4)
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#define FIL_ALL (u_short) (0x8)
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#define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
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#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
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#define SET_TX_START_THRESH (u_short) (0x13<<11)
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#define STATS_ENABLE (u_short) (0x15<<11)
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#define STATS_DISABLE (u_short) (0x16<<11)
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#define STOP_TRANSCEIVER (u_short) (0x17<<11)
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/*
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* The following C_* acknowledge the various interrupts. Some of them don't
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* do anything. See the manual.
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*/
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#define ACK_INTR (u_short) (0x6800)
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#define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
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#define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
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#define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
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#define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
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#define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
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#define C_RX_EARLY (u_short) (ACK_INTR|0x20)
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#define C_INT_RQD (u_short) (ACK_INTR|0x40)
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#define C_UPD_STATS (u_short) (ACK_INTR|0x80)
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#define C_MASK (u_short) 0xFF /* mask of C_* */
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|
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/*
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293 |
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* Status register. All windows.
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294 |
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*
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295 |
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* 15-13: Window number(0-7).
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* 12: Command_in_progress.
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* 11: reserved.
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* 10: reserved.
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* 9: reserved.
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* 8: reserved.
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301 |
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* 7: Update Statistics.
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302 |
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* 6: Interrupt Requested.
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* 5: RX Early.
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* 4: RX Complete.
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* 3: TX Available.
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* 2: TX Complete.
|
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* 1: Adapter Failure.
|
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* 0: Interrupt Latch.
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*/
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#define S_INTR_LATCH (u_short) (0x1)
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311 |
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#define S_CARD_FAILURE (u_short) (0x2)
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#define S_TX_COMPLETE (u_short) (0x4)
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313 |
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#define S_TX_AVAIL (u_short) (0x8)
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#define S_RX_COMPLETE (u_short) (0x10)
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315 |
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#define S_RX_EARLY (u_short) (0x20)
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#define S_INT_RQD (u_short) (0x40)
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#define S_UPD_STATS (u_short) (0x80)
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#define S_MASK (u_short) 0xFF /* mask of S_* */
|
319 |
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#define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
|
320 |
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S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
|
321 |
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#define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
|
322 |
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|
323 |
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/* Address Config. Register.
|
324 |
|
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* Window 0/Port 06
|
325 |
|
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*/
|
326 |
|
|
|
327 |
|
|
#define ACF_CONNECTOR_BITS 14
|
328 |
|
|
#define ACF_CONNECTOR_UTP 0
|
329 |
|
|
#define ACF_CONNECTOR_AUI 1
|
330 |
|
|
#define ACF_CONNECTOR_BNC 3
|
331 |
|
|
|
332 |
|
|
/* Resource configuration register.
|
333 |
|
|
* Window 0/Port 08
|
334 |
|
|
*
|
335 |
|
|
*/
|
336 |
|
|
|
337 |
|
|
#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \
|
338 |
|
|
((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
|
339 |
|
|
((u_short)(irq)<<12)) ) /* set IRQ i */
|
340 |
|
|
|
341 |
|
|
/*
|
342 |
|
|
* FIFO Registers.
|
343 |
|
|
* RX Status. Window 1/Port 08
|
344 |
|
|
*
|
345 |
|
|
* 15: Incomplete or FIFO empty.
|
346 |
|
|
* 14: 1: Error in RX Packet 0: Incomplete or no error.
|
347 |
|
|
* 13-11: Type of error.
|
348 |
|
|
* 1000 = Overrun.
|
349 |
|
|
* 1011 = Run Packet Error.
|
350 |
|
|
* 1100 = Alignment Error.
|
351 |
|
|
* 1101 = CRC Error.
|
352 |
|
|
* 1001 = Oversize Packet Error (>1514 bytes)
|
353 |
|
|
* 0010 = Dribble Bits.
|
354 |
|
|
* (all other error codes, no errors.)
|
355 |
|
|
*
|
356 |
|
|
* 10-0: RX Bytes (0-1514)
|
357 |
|
|
*/
|
358 |
|
|
#define ERR_RX_INCOMPLETE (u_short) (0x1<<15)
|
359 |
|
|
#define ERR_RX (u_short) (0x1<<14)
|
360 |
|
|
#define ERR_RX_OVERRUN (u_short) (0x8<<11)
|
361 |
|
|
#define ERR_RX_RUN_PKT (u_short) (0xb<<11)
|
362 |
|
|
#define ERR_RX_ALIGN (u_short) (0xc<<11)
|
363 |
|
|
#define ERR_RX_CRC (u_short) (0xd<<11)
|
364 |
|
|
#define ERR_RX_OVERSIZE (u_short) (0x9<<11)
|
365 |
|
|
#define ERR_RX_DRIBBLE (u_short) (0x2<<11)
|
366 |
|
|
|
367 |
|
|
/*
|
368 |
|
|
* FIFO Registers.
|
369 |
|
|
* TX Status. Window 1/Port 0B
|
370 |
|
|
*
|
371 |
|
|
* Reports the transmit status of a completed transmission. Writing this
|
372 |
|
|
* register pops the transmit completion stack.
|
373 |
|
|
*
|
374 |
|
|
* Window 1/Port 0x0b.
|
375 |
|
|
*
|
376 |
|
|
* 7: Complete
|
377 |
|
|
* 6: Interrupt on successful transmission requested.
|
378 |
|
|
* 5: Jabber Error (TP Only, TX Reset required. )
|
379 |
|
|
* 4: Underrun (TX Reset required. )
|
380 |
|
|
* 3: Maximum Collisions.
|
381 |
|
|
* 2: TX Status Overflow.
|
382 |
|
|
* 1-0: Undefined.
|
383 |
|
|
*
|
384 |
|
|
*/
|
385 |
|
|
#define TXS_COMPLETE 0x80
|
386 |
|
|
#define TXS_SUCCES_INTR_REQ 0x40
|
387 |
|
|
#define TXS_JABBER 0x20
|
388 |
|
|
#define TXS_UNDERRUN 0x10
|
389 |
|
|
#define TXS_MAX_COLLISION 0x8
|
390 |
|
|
#define TXS_STATUS_OVERFLOW 0x4
|
391 |
|
|
|
392 |
|
|
/*
|
393 |
|
|
* Configuration control register.
|
394 |
|
|
* Window 0/Port 04
|
395 |
|
|
*/
|
396 |
|
|
/* Read */
|
397 |
|
|
#define IS_AUI (1<<13)
|
398 |
|
|
#define IS_BNC (1<<12)
|
399 |
|
|
#define IS_UTP (1<<9)
|
400 |
|
|
/* Write */
|
401 |
|
|
#define ENABLE_DRQ_IRQ 0x0001
|
402 |
|
|
#define W0_P4_CMD_RESET_ADAPTER 0x4
|
403 |
|
|
#define W0_P4_CMD_ENABLE_ADAPTER 0x1
|
404 |
|
|
/*
|
405 |
|
|
* Media type and status.
|
406 |
|
|
* Window 4/Port 0A
|
407 |
|
|
*/
|
408 |
|
|
#define ENABLE_UTP 0xc0
|
409 |
|
|
#define DISABLE_UTP 0x0
|
410 |
|
|
|
411 |
|
|
/*
|
412 |
|
|
* Misc defines for various things.
|
413 |
|
|
*/
|
414 |
|
|
#define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
|
415 |
|
|
#define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
|
416 |
|
|
#define PROD_ID 0x9150
|
417 |
|
|
|
418 |
|
|
#define AUI 0x1
|
419 |
|
|
#define BNC 0x2
|
420 |
|
|
#define UTP 0x4
|
421 |
|
|
|
422 |
|
|
#define RX_BYTES_MASK (u_short) (0x07ff)
|
423 |
|
|
|