| 1 |
30 |
unneback |
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| 2 |
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/* Register descriptions */
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| 3 |
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/* Controller DP8390. */
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| 4 |
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| 5 |
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#define DATAPORT 0x10 /* Port Window. */
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| 6 |
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#define RESET 0x1f /* Issue a read for reset */
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| 7 |
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#define W83CREG 0x00 /* I/O port definition */
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| 8 |
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#define ADDROM 0x08
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| 9 |
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| 10 |
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/* page 0 read or read/write registers */
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| 11 |
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| 12 |
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#define CMDR 0x00+RO
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| 13 |
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#define CLDA0 0x01+RO /* current local dma addr 0 for read */
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| 14 |
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#define CLDA1 0x02+RO /* current local dma addr 1 for read */
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| 15 |
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#define BNRY 0x03+RO /* boundary reg for rd and wr */
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| 16 |
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#define TSR 0x04+RO /* tx status reg for rd */
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| 17 |
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#define NCR 0x05+RO /* number of collision reg for rd */
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| 18 |
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#define FIFO 0x06+RO /* FIFO for rd */
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| 19 |
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#define ISR 0x07+RO /* interrupt status reg for rd and wr */
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| 20 |
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#define CRDA0 0x08+RO /* current remote dma address 0 for rd */
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| 21 |
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#define CRDA1 0x09+RO /* current remote dma address 1 for rd */
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| 22 |
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#define RSR 0x0C+RO /* rx status reg for rd */
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| 23 |
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#define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */
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| 24 |
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#define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */
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| 25 |
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#define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */
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| 26 |
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| 27 |
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/* page 0 write registers */
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| 28 |
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| 29 |
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#define PSTART 0x01+RO /* page start register */
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| 30 |
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#define PSTOP 0x02+RO /* page stop register */
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| 31 |
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#define TPSR 0x04+RO /* tx start page start reg */
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| 32 |
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#define TBCR0 0x05+RO /* tx byte count 0 reg */
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| 33 |
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#define TBCR1 0x06+RO /* tx byte count 1 reg */
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| 34 |
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#define RSAR0 0x08+RO /* remote start address reg 0 */
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| 35 |
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#define RSAR1 0x09+RO /* remote start address reg 1 */
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| 36 |
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#define RBCR0 0x0A+RO /* remote byte count reg 0 */
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| 37 |
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#define RBCR1 0x0B+RO /* remote byte count reg 1 */
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| 38 |
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#define RCR 0x0C+RO /* rx configuration reg */
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| 39 |
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#define TCR 0x0D+RO /* tx configuration reg */
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| 40 |
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#define DCR RO+0x0E /* data configuration reg */
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| 41 |
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#define IMR 0x0F+RO /* interrupt mask reg */
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| 42 |
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| 43 |
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/* page 1 registers */
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| 44 |
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| 45 |
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#define PAR 0x01+RO /* physical addr reg base for rd and wr */
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| 46 |
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#define CURR 0x07+RO /* current page reg for rd and wr */
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| 47 |
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#define MAR 0x08+RO /* multicast addr reg base fro rd and WR */
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| 48 |
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#define MARsize 8 /* size of multicast addr space */
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| 49 |
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| 50 |
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/*-----W83CREG command bits-----*/
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| 51 |
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#define MSK_RESET 0x80 /* W83CREG masks */
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| 52 |
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#define MSK_ENASH 0x40
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| 53 |
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#define MSK_DECOD 0x3F /* memory decode bits, corresponding */
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| 54 |
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/* to SA 18-13. SA 19 assumed to be 1 */
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| 55 |
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| 56 |
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/*-----CMDR command bits-----*/
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| 57 |
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#define MSK_STP 0x01 /* stop the chip */
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| 58 |
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#define MSK_STA 0x02 /* start the chip */
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| 59 |
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#define MSK_TXP 0x04 /* initial txing of a frm */
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| 60 |
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#define MSK_RRE 0x08 /* remote read */
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| 61 |
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#define MSK_RWR 0x10 /* remote write */
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| 62 |
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#define MSK_RD2 0x20 /* no DMA used */
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| 63 |
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#define MSK_PG0 0x00 /* select register page 0 */
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| 64 |
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#define MSK_PG1 0x40 /* select register page 1 */
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| 65 |
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#define MSK_PG2 0x80 /* select register page 2 */
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| 66 |
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| 67 |
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/*-----ISR and TSR status bits-----*/
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| 68 |
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#define MSK_PRX 0x01 /* rx with no error */
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| 69 |
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#define MSK_PTX 0x02 /* tx with no error */
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| 70 |
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#define MSK_RXE 0x04 /* rx with error */
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| 71 |
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#define MSK_TXE 0x08 /* tx with error */
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| 72 |
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#define MSK_OVW 0x10 /* overwrite warning */
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| 73 |
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#define MSK_CNT 0x20 /* MSB of one of the tally counters is set */
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| 74 |
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#define MSK_RDC 0x40 /* remote dma completed */
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| 75 |
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#define MSK_RST 0x80 /* reset state indicator */
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| 76 |
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| 77 |
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/*-----DCR command bits-----*/
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| 78 |
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#define MSK_WTS 0x01 /* word transfer mode selection */
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| 79 |
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#define MSK_BOS 0x02 /* byte order selection */
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| 80 |
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#define MSK_LAS 0x04 /* long addr selection */
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| 81 |
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#define MSK_BMS 0x08 /* burst mode selection */
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| 82 |
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#define MSK_ARM 0x10 /* autoinitialize remote */
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| 83 |
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#define MSK_FT00 0x00 /* burst lrngth selection */
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| 84 |
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#define MSK_FT01 0x20 /* burst lrngth selection */
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| 85 |
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#define MSK_FT10 0x40 /* burst lrngth selection */
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| 86 |
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#define MSK_FT11 0x60 /* burst lrngth selection */
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| 87 |
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| 88 |
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/*-----RCR command bits-----*/
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| 89 |
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#define MSK_SEP 0x01 /* save error pkts */
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| 90 |
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#define MSK_AR 0x02 /* accept runt pkt */
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| 91 |
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#define MSK_AB 0x04 /* 8390 RCR */
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| 92 |
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#define MSK_AM 0x08 /* accept multicast */
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| 93 |
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#define MSK_PRO 0x10 /* accept all pkt with physical adr */
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| 94 |
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#define MSK_MON 0x20 /* monitor mode */
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| 95 |
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| 96 |
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/*-----TCR command bits-----*/
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| 97 |
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#define MSK_CRC 0x01 /* inhibit CRC, do not append crc */
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| 98 |
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#define MSK_LOOP 0x02 /* set loopback mode */
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| 99 |
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#define MSK_BCST 0x04 /* Accept broadcasts */
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| 100 |
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#define MSK_LB01 0x06 /* encoded loopback control */
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| 101 |
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#define MSK_ATD 0x08 /* auto tx disable */
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| 102 |
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#define MSK_OFST 0x10 /* collision offset enable */
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| 103 |
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| 104 |
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/*-----receive status bits-----*/
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| 105 |
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#define SMK_PRX 0x01 /* rx without error */
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| 106 |
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#define SMK_CRC 0x02 /* CRC error */
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| 107 |
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#define SMK_FAE 0x04 /* frame alignment error */
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| 108 |
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#define SMK_FO 0x08 /* FIFO overrun */
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| 109 |
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#define SMK_MPA 0x10 /* missed pkt */
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| 110 |
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#define SMK_PHY 0x20 /* physical/multicase address */
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| 111 |
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#define SMK_DIS 0x40 /* receiver disable. set in monitor mode */
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| 112 |
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#define SMK_DEF 0x80 /* deferring */
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| 113 |
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| 114 |
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/*-----transmit status bits-----*/
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| 115 |
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#define SMK_PTX 0x01 /* tx without error */
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| 116 |
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#define SMK_DFR 0x02 /* non deferred tx */
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| 117 |
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#define SMK_COL 0x04 /* tx collided */
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| 118 |
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#define SMK_ABT 0x08 /* tx abort because of excessive collisions */
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| 119 |
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#define SMK_CRS 0x10 /* carrier sense lost */
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| 120 |
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#define SMK_FU 0x20 /* FIFO underrun */
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| 121 |
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#define SMK_CDH 0x40 /* collision detect heartbeat */
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| 122 |
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#define SMK_OWC 0x80 /* out of window collision */
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| 123 |
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