URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i386/] [ts_386ex/] [start/] [80386ex.inc] - Blame information for rev 173

Details | Compare with Previous | View Log


/*
 *  Submitted by:
 *
 *    Erik Ivanenko
 *    University of Toronto
 *    erik.ivanenko@utoronto.ca
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: 80386ex.inc,v 1.2 2001-09-27 11:59:50 chris Exp $
 */
 
/* REMAP ADDRESSING Registers */
.set REMAPCFGH   , 0x0023
.set REMAPCFGL   , 0x0022
.set REMAPCFG    , 0x0022
/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
.set ICW1M       , 0xF020
.set ICW1S       , 0xF0A0
.set ICW2M       , 0xF021
.set ICW2S       , 0xF0A1
.set ICW3M       , 0xF021
.set ICW3S       , 0xF0A1
.set ICW4M       , 0xF021
.set ICW4S       , 0xF0A1
.set OCW1M       , 0xF021
.set OCW1S       , 0xF0A1
.set OCW2M       , 0xF020
.set OCW2S       , 0xF0A0
.set OCW3M       , 0xF020
.set OCW3S       , 0xF0A0
/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
.set ICW1MDOS    , 0x0020
.set ICW1SDOS    , 0x00A0
.set ICW2MDOS    , 0x0021
.set ICW2SDOS    , 0x00A1
.set ICW3MDOS    , 0x0021
.set ICW3SDOS    , 0x00A1
.set ICW4MDOS    , 0x0021
.set ICW4SDOS    , 0x00A1
.set OCW1MDOS    , 0x0021
.set OCW1SDOS    , 0x00A1
.set OCW2MDOS    , 0x0020
.set OCW2SDOS    , 0x00A0
.set OCW3MDOS    , 0x0020
.set OCW3SDOS    , 0x00A0
 
 
/* CONFIGURATION Registers */
.set DMACFG      , 0xF830
.set INTCFG      , 0xF832
.set TMRCFG      , 0xF834
.set SIOCFG      , 0xF836
.set P1CFG       , 0xF820
.set P2CFG       , 0xF822
.set P3CFG       , 0xF824
.set PINCFG      , 0xF826
 
/* WATCHDOG TIMER Registers */
.set WDTRLDH     , 0xF4C0
.set WDTRLDL     , 0xF4C2
.set WDTCNTH     , 0xF4C4
.set WDTCNTL     , 0xF4C6
.set WDTCLR      , 0xF4C8
.set WDTSTATUS   , 0xF4CA
 
/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
.set TMR0        , 0xF040
.set TMR1        , 0xF041
.set TMR2        , 0xF042
.set TMRCON      , 0xF043
/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
.set TMR0DOS     , 0x0040
.set TMR1DOS     , 0x0041
.set TMR2DOS     , 0x0042
.set TMRCONDOS   , 0x0043
 
/* INPUT/OUTPUT PORT UNIT Registers */
.set P1PIN       , 0xF860
.set P1LTC       , 0xF862
.set P1DIR       , 0xF864
.set P2PIN       , 0xF868
.set P2LTC       , 0xF86A
.set P2DIR       , 0xF86C
.set P3PIN       , 0xF870
.set P3LTC       , 0xF872
.set P3DIR       , 0xF874
 
/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
.set RBR0        , 0xF4F8
.set THR0        , 0xF4F8
.set TBR0        , 0xF4F8
.set DLL0        , 0xF4F8
.set IER0        , 0xF4F9
.set DLH0        , 0xF4F9
.set IIR0        , 0xF4FA
.set LCR0        , 0xF4FB
.set MCR0        , 0xF4FC
.set LSR0        , 0xF4FD
.set MSR0        , 0xF4FE
.set SCR0        , 0xF4FF
/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
.set RBR0DOS     , 0x03F8
.set THR0DOS     , 0x03F8
.set TBR0DOS     , 0x03F8
.set DLL0DOS     , 0x03F8
.set IER0DOS     , 0x03F9
.set DLH0DOS     , 0x03F9
.set IIR0DOS     , 0x03FA
.set LCR0DOS     , 0x03FB
.set MCR0DOS     , 0x03FC
.set LSR0DOS     , 0x03FD
.set MSR0DOS     , 0x03FE
.set SCR0DOS     , 0x03FF
 
/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
.set RBR1        , 0xF8F8
.set THR1        , 0xF8F8
.set TBR1        , 0XF8F8
.set DLL1        , 0xF8F8
.set IER1        , 0xF8F9
.set DLH1        , 0xF8F9
.set IIR1        , 0xF8FA
.set LCR1        , 0xF8FB
.set MCR1        , 0xF8FC
.set LSR1        , 0xF8FD
.set MSR1        , 0xF8FE
.set SCR1        , 0xF8FF
/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
.set RBR1DOS     , 0x02F8
.set THR1DOS     , 0x02F8
.set TBR1DOS     , 0x02F8
.set DLL1DOS     , 0x02F8
.set IER1DOS     , 0x02F9
.set DLH1DOS     , 0x02F9
.set IIR1DOS     , 0x02FA
.set LCR1DOS     , 0x02FB
.set MCR1DOS     , 0x02FC
.set LSR1DOS     , 0x02FD
.set MSR1DOS     , 0x02FE
.set SCR1DOS     , 0x02FF
 
/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
.set SSIOTBUF    , 0xF480
.set SSIORBUF    , 0xF482
.set SSIOBAUD    , 0xF484
.set SSIOCON1    , 0xF486
.set SSIOCON2    , 0xF488
.set SSIOCTR     , 0xF48A
 
/* CHIP SELECT UNIT Registers */
.set CS0ADL      , 0xF400
.set CS0ADH      , 0xF402
.set CS0MSKL     , 0xF404
.set CS0MSKH     , 0xF406
.set CS1ADL      , 0xF408
.set CS1ADH      , 0xF40A
.set CS1MSKL     , 0xF40C
.set CS1MSKH     , 0xF40E
.set CS2ADL      , 0xF410
.set CS2ADH      , 0xF412
.set CS2MSKL     , 0xF414
.set CS2MSKH     , 0xF416
.set CS3ADL      , 0xF418
.set CS3ADH      , 0xF41A
.set CS3MSKL     , 0xF41C
.set CS3MSKH     , 0xF41E
.set CS4ADL      , 0xF420
.set CS4ADH      , 0xF422
.set CS4MSKL     , 0xF424
.set CS4MSKH     , 0xF426
.set CS5ADL      , 0xF428
.set CS5ADH      , 0xF42A
.set CS5MSKL     , 0xF42C
.set CS5MSKH     , 0xF42E
.set CS6ADL      , 0xF430
.set CS6ADH      , 0xF432
.set CS6MSKL     , 0xF434
.set CS6MSKH     , 0xF436
.set UCSADL      , 0xF438
.set UCSADH      , 0xF43A
.set UCSMSKL     , 0xF43C
.set UCSMSKH     , 0xF43E
 
/* REFRESH CONTROL UNIT Registers */
 
.set RFSBAD      , 0xF4A0
.set RFSCIR      , 0xF4A2
.set RFSCON      , 0xF4A4
.set RFSADD      , 0xF4A6
 
/* POWER MANAGEMENT CONTROL Registers */
 
.set PWRCON      , 0xF800
.set CLKPRS      , 0xF804
 
/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
.set DMA0TAR     , 0xF000
.set DMA0BYC     , 0xF001
.set DMA1TAR     , 0xF002
.set DMA1BYC     , 0xF003
.set DMACMD1     , 0xF008
.set DMASTS      , 0xF008
.set DMASRR      , 0xF009
.set DMAMSK      , 0xF00A
.set DMAMOD1     , 0xF00B
.set DMACLRBP    , 0xF00C
.set DMACLR      , 0xF00D
.set DMACLRMSK   , 0xF00E
.set DMAGRPMSK   , 0xF00F
.set DMA0REQL    , 0xF010
.set DMA0REQH    , 0xF011
.set DMA1REQL    , 0xF012
.set DMA1REQH    , 0xF013
.set DMABSR      , 0xF018
.set DMACHR      , 0xF019
.set DMAIS       , 0xF019
.set DMACMD2     , 0xF01A
.set DMAMOD2     , 0xF01B
.set DMAIEN      , 0xF01C
.set DMAOVFE     , 0xF01D
.set DMACLRTC    , 0xF01E
.set DMA1TARPL   , 0xF083
.set DMA1TARPH   , 0xF085
.set DMA0TARPH   , 0xF086
.set DMA0TARPL   , 0xF087
.set DMA0BYCH    , 0xF098
.set DMA1BYCH    , 0xF099
 
/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
.set DMA0TARDOS  , 0x0000
.set DMA0BYCDOS  , 0x0001
.set DMA1TARDOS  , 0x0002
.set DMA1BYCDOS  , 0x0003
.set DMACMD1DOS  , 0x0008
.set DMASTSDOS   , 0x0008
.set DMASRRDOS   , 0x0009
.set DMAMSKDOS   , 0x000A
.set DMAMOD1DOS  , 0x000B
.set DMACLRBPDOS , 0x000C
.set DMACLRDOS   , 0x000D
.set DMACLRMSKDOS  , 0x000E
.set DMAGRPMSKDOS  , 0x000F
.set DMA1TARPLDOS  , 0x0083
.set DMA0TARPLDOS  , 0x0087
 
/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
.set PORT92      , 0xF092
/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
.set PORT92DOS   , 0x0092

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i386/] [ts_386ex/] [start/] [80386ex.inc] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* Submitted by:`
3			`*`
4			`* Erik Ivanenko`
5			`* University of Toronto`
6			`* erik.ivanenko@utoronto.ca`
7			`*`
8			`* The license and distribution terms for this file may be`
9			`* found in the file LICENSE in this distribution or at`
10			`* http://www.OARcorp.com/rtems/license.html.`
11			`*`
12			`* $Id: 80386ex.inc,v 1.2 2001-09-27 11:59:50 chris Exp $`
13			`*/`
14
15			`/* REMAP ADDRESSING Registers */`
16			`.set REMAPCFGH , 0x0023`
17			`.set REMAPCFGL , 0x0022`
18			`.set REMAPCFG , 0x0022`
19			`/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */`
20			`.set ICW1M , 0xF020`
21			`.set ICW1S , 0xF0A0`
22			`.set ICW2M , 0xF021`
23			`.set ICW2S , 0xF0A1`
24			`.set ICW3M , 0xF021`
25			`.set ICW3S , 0xF0A1`
26			`.set ICW4M , 0xF021`
27			`.set ICW4S , 0xF0A1`
28			`.set OCW1M , 0xF021`
29			`.set OCW1S , 0xF0A1`
30			`.set OCW2M , 0xF020`
31			`.set OCW2S , 0xF0A0`
32			`.set OCW3M , 0xF020`
33			`.set OCW3S , 0xF0A0`
34			`/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */`
35			`.set ICW1MDOS , 0x0020`
36			`.set ICW1SDOS , 0x00A0`
37			`.set ICW2MDOS , 0x0021`
38			`.set ICW2SDOS , 0x00A1`
39			`.set ICW3MDOS , 0x0021`
40			`.set ICW3SDOS , 0x00A1`
41			`.set ICW4MDOS , 0x0021`
42			`.set ICW4SDOS , 0x00A1`
43			`.set OCW1MDOS , 0x0021`
44			`.set OCW1SDOS , 0x00A1`
45			`.set OCW2MDOS , 0x0020`
46			`.set OCW2SDOS , 0x00A0`
47			`.set OCW3MDOS , 0x0020`
48			`.set OCW3SDOS , 0x00A0`
49
50
51			`/* CONFIGURATION Registers */`
52			`.set DMACFG , 0xF830`
53			`.set INTCFG , 0xF832`
54			`.set TMRCFG , 0xF834`
55			`.set SIOCFG , 0xF836`
56			`.set P1CFG , 0xF820`
57			`.set P2CFG , 0xF822`
58			`.set P3CFG , 0xF824`
59			`.set PINCFG , 0xF826`
60
61			`/* WATCHDOG TIMER Registers */`
62			`.set WDTRLDH , 0xF4C0`
63			`.set WDTRLDL , 0xF4C2`
64			`.set WDTCNTH , 0xF4C4`
65			`.set WDTCNTL , 0xF4C6`
66			`.set WDTCLR , 0xF4C8`
67			`.set WDTSTATUS , 0xF4CA`
68
69			`/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */`
70			`.set TMR0 , 0xF040`
71			`.set TMR1 , 0xF041`
72			`.set TMR2 , 0xF042`
73			`.set TMRCON , 0xF043`
74			`/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */`
75			`.set TMR0DOS , 0x0040`
76			`.set TMR1DOS , 0x0041`
77			`.set TMR2DOS , 0x0042`
78			`.set TMRCONDOS , 0x0043`
79
80			`/* INPUT/OUTPUT PORT UNIT Registers */`
81			`.set P1PIN , 0xF860`
82			`.set P1LTC , 0xF862`
83			`.set P1DIR , 0xF864`
84			`.set P2PIN , 0xF868`
85			`.set P2LTC , 0xF86A`
86			`.set P2DIR , 0xF86C`
87			`.set P3PIN , 0xF870`
88			`.set P3LTC , 0xF872`
89			`.set P3DIR , 0xF874`
90
91			`/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */`
92			`.set RBR0 , 0xF4F8`
93			`.set THR0 , 0xF4F8`
94			`.set TBR0 , 0xF4F8`
95			`.set DLL0 , 0xF4F8`
96			`.set IER0 , 0xF4F9`
97			`.set DLH0 , 0xF4F9`
98			`.set IIR0 , 0xF4FA`
99			`.set LCR0 , 0xF4FB`
100			`.set MCR0 , 0xF4FC`
101			`.set LSR0 , 0xF4FD`
102			`.set MSR0 , 0xF4FE`
103			`.set SCR0 , 0xF4FF`
104			`/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */`
105			`.set RBR0DOS , 0x03F8`
106			`.set THR0DOS , 0x03F8`
107			`.set TBR0DOS , 0x03F8`
108			`.set DLL0DOS , 0x03F8`
109			`.set IER0DOS , 0x03F9`
110			`.set DLH0DOS , 0x03F9`
111			`.set IIR0DOS , 0x03FA`
112			`.set LCR0DOS , 0x03FB`
113			`.set MCR0DOS , 0x03FC`
114			`.set LSR0DOS , 0x03FD`
115			`.set MSR0DOS , 0x03FE`
116			`.set SCR0DOS , 0x03FF`
117
118			`/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */`
119			`.set RBR1 , 0xF8F8`
120			`.set THR1 , 0xF8F8`
121			`.set TBR1 , 0XF8F8`
122			`.set DLL1 , 0xF8F8`
123			`.set IER1 , 0xF8F9`
124			`.set DLH1 , 0xF8F9`
125			`.set IIR1 , 0xF8FA`
126			`.set LCR1 , 0xF8FB`
127			`.set MCR1 , 0xF8FC`
128			`.set LSR1 , 0xF8FD`
129			`.set MSR1 , 0xF8FE`
130			`.set SCR1 , 0xF8FF`
131			`/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */`
132			`.set RBR1DOS , 0x02F8`
133			`.set THR1DOS , 0x02F8`
134			`.set TBR1DOS , 0x02F8`
135			`.set DLL1DOS , 0x02F8`
136			`.set IER1DOS , 0x02F9`
137			`.set DLH1DOS , 0x02F9`
138			`.set IIR1DOS , 0x02FA`
139			`.set LCR1DOS , 0x02FB`
140			`.set MCR1DOS , 0x02FC`
141			`.set LSR1DOS , 0x02FD`
142			`.set MSR1DOS , 0x02FE`
143			`.set SCR1DOS , 0x02FF`
144
145			`/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */`
146			`.set SSIOTBUF , 0xF480`
147			`.set SSIORBUF , 0xF482`
148			`.set SSIOBAUD , 0xF484`
149			`.set SSIOCON1 , 0xF486`
150			`.set SSIOCON2 , 0xF488`
151			`.set SSIOCTR , 0xF48A`
152
153			`/* CHIP SELECT UNIT Registers */`
154			`.set CS0ADL , 0xF400`
155			`.set CS0ADH , 0xF402`
156			`.set CS0MSKL , 0xF404`
157			`.set CS0MSKH , 0xF406`
158			`.set CS1ADL , 0xF408`
159			`.set CS1ADH , 0xF40A`
160			`.set CS1MSKL , 0xF40C`
161			`.set CS1MSKH , 0xF40E`
162			`.set CS2ADL , 0xF410`
163			`.set CS2ADH , 0xF412`
164			`.set CS2MSKL , 0xF414`
165			`.set CS2MSKH , 0xF416`
166			`.set CS3ADL , 0xF418`
167			`.set CS3ADH , 0xF41A`
168			`.set CS3MSKL , 0xF41C`
169			`.set CS3MSKH , 0xF41E`
170			`.set CS4ADL , 0xF420`
171			`.set CS4ADH , 0xF422`
172			`.set CS4MSKL , 0xF424`
173			`.set CS4MSKH , 0xF426`
174			`.set CS5ADL , 0xF428`
175			`.set CS5ADH , 0xF42A`
176			`.set CS5MSKL , 0xF42C`
177			`.set CS5MSKH , 0xF42E`
178			`.set CS6ADL , 0xF430`
179			`.set CS6ADH , 0xF432`
180			`.set CS6MSKL , 0xF434`
181			`.set CS6MSKH , 0xF436`
182			`.set UCSADL , 0xF438`
183			`.set UCSADH , 0xF43A`
184			`.set UCSMSKL , 0xF43C`
185			`.set UCSMSKH , 0xF43E`
186
187			`/* REFRESH CONTROL UNIT Registers */`
188
189			`.set RFSBAD , 0xF4A0`
190			`.set RFSCIR , 0xF4A2`
191			`.set RFSCON , 0xF4A4`
192			`.set RFSADD , 0xF4A6`
193
194			`/* POWER MANAGEMENT CONTROL Registers */`
195
196			`.set PWRCON , 0xF800`
197			`.set CLKPRS , 0xF804`
198
199			`/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */`
200			`.set DMA0TAR , 0xF000`
201			`.set DMA0BYC , 0xF001`
202			`.set DMA1TAR , 0xF002`
203			`.set DMA1BYC , 0xF003`
204			`.set DMACMD1 , 0xF008`
205			`.set DMASTS , 0xF008`
206			`.set DMASRR , 0xF009`
207			`.set DMAMSK , 0xF00A`
208			`.set DMAMOD1 , 0xF00B`
209			`.set DMACLRBP , 0xF00C`
210			`.set DMACLR , 0xF00D`
211			`.set DMACLRMSK , 0xF00E`
212			`.set DMAGRPMSK , 0xF00F`
213			`.set DMA0REQL , 0xF010`
214			`.set DMA0REQH , 0xF011`
215			`.set DMA1REQL , 0xF012`
216			`.set DMA1REQH , 0xF013`
217			`.set DMABSR , 0xF018`
218			`.set DMACHR , 0xF019`
219			`.set DMAIS , 0xF019`
220			`.set DMACMD2 , 0xF01A`
221			`.set DMAMOD2 , 0xF01B`
222			`.set DMAIEN , 0xF01C`
223			`.set DMAOVFE , 0xF01D`
224			`.set DMACLRTC , 0xF01E`
225			`.set DMA1TARPL , 0xF083`
226			`.set DMA1TARPH , 0xF085`
227			`.set DMA0TARPH , 0xF086`
228			`.set DMA0TARPL , 0xF087`
229			`.set DMA0BYCH , 0xF098`
230			`.set DMA1BYCH , 0xF099`
231
232			`/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */`
233			`.set DMA0TARDOS , 0x0000`
234			`.set DMA0BYCDOS , 0x0001`
235			`.set DMA1TARDOS , 0x0002`
236			`.set DMA1BYCDOS , 0x0003`
237			`.set DMACMD1DOS , 0x0008`
238			`.set DMASTSDOS , 0x0008`
239			`.set DMASRRDOS , 0x0009`
240			`.set DMAMSKDOS , 0x000A`
241			`.set DMAMOD1DOS , 0x000B`
242			`.set DMACLRBPDOS , 0x000C`
243			`.set DMACLRDOS , 0x000D`
244			`.set DMACLRMSKDOS , 0x000E`
245			`.set DMAGRPMSKDOS , 0x000F`
246			`.set DMA1TARPLDOS , 0x0083`
247			`.set DMA0TARPLDOS , 0x0087`
248
249			`/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */`
250			`.set PORT92 , 0xF092`
251			`/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */`
252			`.set PORT92DOS , 0x0092`