OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i386/] [ts_386ex/] [start/] [macros.inc] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/* macros.inc
2
 *
3
 * This file assists the board independent startup code
4
 * by initializing the chip-select channels to
5
 * reflect the proper memory configuration.
6
 *
7
 * NOTE: No stack has been established when this routine
8
 *       is invoked.  It returns to start.s through ldsegs
9
 *
10
 *  Submitted by:
11
 *
12
 *    Erik Ivanenko
13
 *    University of Toronto
14
 *    erik.ivanenko@utoronto.ca
15
 *
16
 *  The license and distribution terms for this file may be
17
 *  found in the file LICENSE in this distribution or at
18
 *  http://www.OARcorp.com/rtems/license.html.
19
 *
20
 *  $Id: macros.inc,v 1.2 2001-09-27 11:59:50 chris Exp $
21
 */
22
 
23
.set GDT_CODE_PTR       , 0x08
24
.set GDT_DATA_PTR       , 0x10
25
 
26
.set BOARD_SELECT  , 0x301
27
.set BOARD_DATA    , 0x302
28
.set BOARD_LATCH   , 0x303
29
 
30
 
31
#define SetExRegByte(_register,_value) \
32
        movb       $ ## _value, al; \
33
        movw      $ ## _register, dx; \
34
        outb       al, dx
35
 
36
#define SetExRegWord(_register,_value) \
37
        movw      $ ## _value, ax; \
38
        movw      $ ## _register, dx ; \
39
        outw      ax, dx
40
 
41
 
42
#define DESC2(lim_0_15, bas_0_15, bas_16_23, access, gran, bas_24_31) \
43
 .word lim_0_15 ; \
44
 .word bas_0_15 ; \
45
 .byte bas_16_23 ; \
46
 .byte access ; \
47
 .byte gran ; \
48
 .byte bas_24_31
49
 
50
#define DESC3( _base, _limit) \
51
.word _limit ; \
52
.long _base
53
 
54
/* THE GET_ACCESS IS CHANGED FROM 8E TO 9E */
55
 
56
#define INTERRUPT_GATE( _vector ) \
57
        .word   _vector ; \
58
        .word   GDT_CODE_PTR ; \
59
        .byte   0x0 ; \
60
        .byte   0x8E ; \
61
        .word   0x0
62
 
63
#define rLOAD_INDEX( _selector, _segment_register) \
64
        movl     _selector , _segment_register ; \
65
        addb    al, ( eax )
66
 
67
#define rLOAD_SEGMENT( _reg, _segment_register) \
68
        mov     _reg , _segment_register ; \
69
 
70
/* #define rLOAD_SEGMENT( _reg, _segment_register) \
71
        .code16 ; \
72
        mov     _reg , _segment_register ; \
73
        .code32
74
*/
75
#define pLOAD_SEGMENT( _selector, _segment_register) \
76
        movl     $ ##  _selector , eax ; .code16 ; \
77
        mov      ax, _segment_register ; .code32
78
 
79
/* #define MOVE_WORD( _immed32, _reg ) \
80
        data16 ; \
81
        movl    _immed32, _reg
82
*/
83
 
84
#define MOVE_WORD( _immed32, _reg ) \
85
        movw    _immed32, _reg
86
 
87
/* #define MOVE_IMMED_WORD( _immed32, _reg ) \
88
        data16 ; \
89
        mov    $ ## _immed32, _reg
90
 
91
#define CS_OFF( _cs_symbol, _reg ) \
92
        data16 ; \
93
        mov     _cs_symbol, _reg ; \
94
        data16 ;\
95
        andl    $0x000ffff, _reg
96
 
97
#define _16_NOPS \
98
        nop ; \
99
        nop ; \
100
        nop ; \
101
        nop ; \
102
        nop ; \
103
        nop ; \
104
        nop ; \
105
        nop ; \
106
        nop ; \
107
        nop ; \
108
        nop ; \
109
        nop ; \
110
        nop ; \
111
        nop ; \
112
        nop ; \
113
        nop ;
114
*/
115
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.