1 |
30 |
unneback |
/* set_vector
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2 |
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*
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3 |
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* This routine attempts to perform all "generic" interrupt initialization
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4 |
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* for the specified XINT line. It is specific to the Cyclone CVME961 in
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5 |
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* that it knows which interrupts are initialized by the monitor, the
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6 |
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* characteristics of XINT5 (VIC068 clock tick), and that it assumes the
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7 |
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* i960 is processing interrupts in dedicated mode. It attempts to map
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8 |
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* XINTs to interrupt vectors in a fairly straght forward way.
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9 |
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*
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10 |
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* XINT USE VECTOR INTR TBL INDEX TRIGGERED
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11 |
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* ==== ============= ====== ============== =========
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* 0 VMEbus ERROR 0x02 0x03 EDGE
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13 |
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* 1 DRAM PARITY 0x12 0x13 EDGE
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14 |
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* 2 Z8530 0x22 0x23 LEVEL
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15 |
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* 3 SQUALL 0 0x52 0x53 ----
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16 |
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* 4 Z8536 (SQSIO4) 0x72 0x73 LEVEL
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17 |
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* 5 TICK 0x32 0x33 EDGE
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18 |
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* 6 VIC068 0x62 0x63 LEVEL
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19 |
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* 7 UNUSED 0x42 0x43 LEVEL
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20 |
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*
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21 |
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* The interrupt handler is installed in both the cached and memory
|
22 |
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* resident interrupt tables. The appropriate IMAP register is updated to
|
23 |
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* reflect the vector selected by this routine. Global interrupts are
|
24 |
|
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* enabled. If XINT5 is being installed, places it in trigger mode.
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25 |
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* Finally, set_vector_support() is invoked to install the new IMAP and
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26 |
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* ICON, unmask the XINT in IMASK, and lower the i960's interrupt
|
27 |
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* level to 0.
|
28 |
|
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*
|
29 |
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* INPUT:
|
30 |
|
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* func - interrupt handler entry point
|
31 |
|
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* xint - external interrupt line
|
32 |
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* type - 0 indicates raw hardware connect
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33 |
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* 1 indicates RTEMS interrupt connect
|
34 |
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*
|
35 |
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* RETURNS:
|
36 |
|
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* address of previous interrupt handler
|
37 |
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*
|
38 |
|
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* COPYRIGHT (c) 1989-1999.
|
39 |
|
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* On-Line Applications Research Corporation (OAR).
|
40 |
|
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*
|
41 |
|
|
* The license and distribution terms for this file may be
|
42 |
|
|
* found in the file LICENSE in this distribution or at
|
43 |
|
|
* http://www.OARcorp.com/rtems/license.html.
|
44 |
|
|
*
|
45 |
|
|
* $Id: setvec.c,v 1.2 2001-09-27 11:59:57 chris Exp $
|
46 |
|
|
*/
|
47 |
|
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|
48 |
|
|
#include <rtems.h>
|
49 |
|
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#include <bsp.h>
|
50 |
|
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|
51 |
|
|
#include <stdio.h>
|
52 |
|
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|
53 |
|
|
void print_prcb();
|
54 |
|
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void print_intr_info();
|
55 |
|
|
void print_ipnd_imsk();
|
56 |
|
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|
57 |
|
|
unsigned int Xint_2_Group_Map[8] = { 0, 1, 2, 5, 7, 3, 6, 4 };
|
58 |
|
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|
59 |
|
|
i960_isr_entry set_vector( /* returns old vector */
|
60 |
|
|
rtems_isr_entry func, /* isr routine */
|
61 |
|
|
unsigned int xint, /* XINT number */
|
62 |
|
|
unsigned int type /* RTEMS or RAW */
|
63 |
|
|
)
|
64 |
|
|
{
|
65 |
|
|
i960_isr_entry *intr_tbl, *cached_intr_tbl;
|
66 |
|
|
i960_isr_entry saved_intr;
|
67 |
|
|
unsigned int vector, group, nibble;
|
68 |
|
|
unsigned int *imap;
|
69 |
|
|
|
70 |
|
|
if ( xint > 7 )
|
71 |
|
|
exit( 0x80 );
|
72 |
|
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|
73 |
|
|
cached_intr_tbl = (i960_isr_entry *) 0;
|
74 |
|
|
intr_tbl = (i960_isr_entry *) Prcb->intr_tbl;
|
75 |
|
|
group = Xint_2_Group_Map[xint]; /* remap XINT to group */
|
76 |
|
|
vector = (group << 4) + 2; /* direct vector num */
|
77 |
|
|
|
78 |
|
|
if ( type )
|
79 |
|
|
rtems_interrupt_catch( func, vector, (rtems_isr_entry *) &saved_intr );
|
80 |
|
|
else {
|
81 |
|
|
saved_intr = (i960_isr_entry) intr_tbl[ vector ];
|
82 |
|
|
/* return old vector */
|
83 |
|
|
intr_tbl[ vector + 1 ] = /* normal vector table */
|
84 |
|
|
cached_intr_tbl[ group ] = (i960_isr_entry) func; /* cached vector */
|
85 |
|
|
}
|
86 |
|
|
|
87 |
|
|
if ( xint <= 3 ) imap = &Ctl_tbl->imap0; /* updating IMAP0 */
|
88 |
|
|
else imap = &Ctl_tbl->imap1; /* updating IMAP1 */
|
89 |
|
|
nibble = (xint % 4) * 4;
|
90 |
|
|
*imap &= ~(0xf << nibble);
|
91 |
|
|
*imap |= group << nibble;
|
92 |
|
|
|
93 |
|
|
Ctl_tbl->icon &= ~0x00000400; /* enable global interrupts */
|
94 |
|
|
Ctl_tbl->icon |= 0x00004000; /* fast sampling mode */
|
95 |
|
|
switch ( xint ) {
|
96 |
|
|
case 0: Ctl_tbl->icon |= 0x00000004; break;
|
97 |
|
|
case 1: Ctl_tbl->icon |= 0x00000008; break;
|
98 |
|
|
case 2: Ctl_tbl->icon &= ~0x00000010; break;
|
99 |
|
|
case 4: Ctl_tbl->icon &= ~0x00000040; break;
|
100 |
|
|
case 5: Ctl_tbl->icon |= 0x00000080; break;
|
101 |
|
|
case 6: Ctl_tbl->icon &= ~0x00000100; break;
|
102 |
|
|
default: exit( 0x81 ); break; /* unsupported */
|
103 |
|
|
}
|
104 |
|
|
|
105 |
|
|
if ( xint == 4 ) { /* reprogram MCON for SQSIO4 */
|
106 |
|
|
Ctl_tbl->mcon12 = 0x00002012; /* MCON12 - 0xCxxxxxxx */
|
107 |
|
|
Ctl_tbl->mcon13 = 0x00000000; /* MCON13 - 0xDxxxxxxx */
|
108 |
|
|
i960_reload_ctl_group( 5 ); /* update MCON12-MCON15 */
|
109 |
|
|
}
|
110 |
|
|
|
111 |
|
|
i960_unmask_intr( xint ); /* update IMSK */
|
112 |
|
|
i960_reload_ctl_group( 1 ); /* update IMAP?/ICON */
|
113 |
|
|
return( saved_intr ); /* return old vector */
|
114 |
|
|
}
|
115 |
|
|
|
116 |
|
|
void print_prcb()
|
117 |
|
|
{
|
118 |
|
|
printf( "fault_table =0x%p\n", Prcb->fault_tbl );
|
119 |
|
|
printf( "control_tbl =0x%p\n", Prcb->control_tbl );
|
120 |
|
|
printf( "AC mask ov =0x%x\n", Prcb->initial_ac );
|
121 |
|
|
printf( "fltconfig =0x%x\n", Prcb->fault_config );
|
122 |
|
|
printf( "intr tbl =0x%p\n", Prcb->intr_tbl );
|
123 |
|
|
printf( "systable =0x%p\n", Prcb->sys_proc_tbl );
|
124 |
|
|
printf( "reserved =0x%x\n", Prcb->reserved );
|
125 |
|
|
printf( "isr stk =0x%p\n", Prcb->intr_stack );
|
126 |
|
|
printf( "ins cache =0x%x\n", Prcb->ins_cache_cfg );
|
127 |
|
|
printf( "reg cache =0x%x\n", Prcb->reg_cache_cfg );
|
128 |
|
|
}
|
129 |
|
|
|
130 |
|
|
void print_intr_info()
|
131 |
|
|
{
|
132 |
|
|
printf( "prcb =0x%p\n", Prcb );
|
133 |
|
|
printf( "ctl_tbl =0x%p\n", Ctl_tbl );
|
134 |
|
|
printf( "intr_tbl=0x%p\n", Prcb->intr_tbl );
|
135 |
|
|
printf( "IMAP0 = 0x%x\n", Ctl_tbl->imap0 );
|
136 |
|
|
printf( "IMAP1 = 0x%x\n", Ctl_tbl->imap1 );
|
137 |
|
|
print_ipnd_imsk();
|
138 |
|
|
}
|
139 |
|
|
|
140 |
|
|
void print_ipnd_imsk()
|
141 |
|
|
{
|
142 |
|
|
printf(" IPEND = 0x%x\n", i960_pend_intrs() );
|
143 |
|
|
printf(" IMASK = 0x%x\n", i960_mask_intrs() );
|
144 |
|
|
}
|