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/* Timer_init()
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*
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* This routine initializes the Z8536 timer on the SQSIO4 SQUALL
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* board for the CVME961 board. The timer is setup to provide a
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* tick every 1 millisecond.
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*
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* Input parameters: NONE
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*
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* Output parameters: NONE
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*
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* NOTE: This routine will not work if the optimizer is enabled
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* for most compilers. The multiple writes to the Z8536
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* will be optimized away.
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*
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* It is important that the timer start/stop overhead be
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* determined when porting or modifying this code.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: timer.c,v 1.2 2001-09-27 11:59:58 chris Exp $
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*/
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#include <rtems.h>
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#include <bsp.h>
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#include <zilog/z8536.h>
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#define TIMER 0xc00000a0
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int Ttimer_val;
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rtems_boolean Timer_driver_Find_average_overhead;
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void flush_reg();
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rtems_isr timerisr();
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void Timer_initialize()
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{
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set_vector( timerisr, 4, 0 ); /* install ISR */
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i960_mask_intr( 5 ); /* disable VIC068 tick */
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flush_reg(); /* timed code starts clean */
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Ttimer_val = 0; /* clear timer ISR count */
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Z8x36_WRITE( TIMER, MASTER_INTR, 0x01 ); /* reset */
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Z8x36_WRITE( TIMER, MASTER_INTR, 0x00 ); /* clear reset */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0x00 ); /* disable everything */
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Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, 0x72 ); /* clear intr vector */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0x20 ); /* clear intr info */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0xe0 ); /* disable interrupts */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0x20 ); /* clear intr info */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0xe0 ); /* disable interrupts */
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Z8x36_WRITE( TIMER, MASTER_INTR, 0xe2 ); /* disable lower chain, */
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/* no vector, set right */
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/* justified addr and */
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/* master int enable */
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Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x80 ); /* T1 continuous, and */
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/* cycle/pulse output */
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Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x00 );
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Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0x00 );
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Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xc0 ); /* set INTR enable (IE) */
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Z8x36_WRITE( TIMER, MASTER_CFG, 0x40 ); /* enable timer1 */
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Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0x06 ); /* set trigger command */
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/* (TCB) and gate */
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/* command (GCB) bits */
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}
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#define AVG_OVERHEAD 11 /* It typically takes 5.5 microseconds */
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/* (11 countdowns) to start/stop the timer. */
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#define LEAST_VALID 15 /* Don't trust a value lower than this */
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int Read_timer()
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{
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rtems_unsigned8 msb, lsb;
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rtems_unsigned32 remaining, total;
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Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xce ); /* read the counter value */
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Z8x36_READ( TIMER, CT1_CUR_CNT_MSB, msb );
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Z8x36_READ( TIMER, CT1_CUR_CNT_LSB, lsb );
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remaining = 0xffff - ((msb << 8) + lsb);
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total = (Ttimer_val * 0x10000) + remaining;
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if ( Timer_driver_Find_average_overhead == 1 )
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return total; /* in one-half microsecond units */
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else {
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if ( total < LEAST_VALID )
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return 0; /* below timer resolution */
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return (total-AVG_OVERHEAD) >> 1;
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}
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}
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rtems_status_code Empty_function( void )
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{
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return RTEMS_SUCCESSFUL;
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}
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void Set_find_average_overhead(
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rtems_boolean find_flag
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)
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{
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Timer_driver_Find_average_overhead = find_flag;
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}
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