OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i960/] [rxgen960/] [include/] [rxgen960_config.h] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  PMC901 specific configuration values
3
 *
4
 *  $Id: rxgen960_config.h,v 1.2 2001-09-27 11:59:59 chris Exp $
5
 */
6
 
7
#ifndef  __PMC901_CONFIG__
8
#define __PMC901_CONFIG__
9
/* The following define the PMC960 bus regions */
10
/* Bus configuration */
11
#define RP_CONFIG_REGS     I960RP_BUS_WIDTH(32)
12
#define FLASH              I960RP_BUS_WIDTH(8)
13
#define DRAM               I960RP_BUS_WIDTH(32)
14
#define UART_LED           I960RP_BUS_WIDTH(8)
15
#define DEFAULT            I960RP_BUS_WIDTH(32)
16
 
17
/* Region Configuration */
18
#define  REGION_0_CONFIG      RP_CONFIG_REGS
19
#define  REGION_2_CONFIG      DEFAULT
20
#define  REGION_4_CONFIG      DEFAULT
21
#define  REGION_6_CONFIG      DEFAULT
22
#define  REGION_8_CONFIG      DEFAULT
23
#define  REGION_A_CONFIG      DRAM
24
#define  REGION_C_CONFIG      UART_LED
25
#define  REGION_E_CONFIG      DEFAULT
26
/* #define  REGION_BOOT_CONFIG   (FLASH | I960RP_ZBYTE_ORDER)*/
27
#define  REGION_BOOT_CONFIG   (DRAM)
28
 
29
/* #define  DRAM_BASE   0xfed00000 */
30
#define  DRAM_BASE      0xa0000000
31
 
32
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.