OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i960/] [rxgen960/] [shmsupp/] [getcfg.c] - Blame information for rev 814

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  void Shm_Get_configuration( localnode, &shmcfg )
2
 *
3
 *  This routine initializes, if necessary, and returns a pointer
4
 *  to the Shared Memory Configuration Table for the Cyclone CVME961.
5
 *
6
 *  INPUT PARAMETERS:
7
 *    localnode - local node number
8
 *    shmcfg    - address of pointer to SHM Config Table
9
 *
10
 *  OUTPUT PARAMETERS:
11
 *    *shmcfg   - pointer to SHM Config Table
12
 *
13
 *  NOTES:  CVME961 target system has onboard dual-ported memory.  This
14
 *          file uses the USE_ONBOARD_RAM macro to determine if this
15
 *          RAM is to be used as the SHM.  If so (i.e. USE_ONBOARD_RAM
16
 *          is set to 1), it is assumed that the master node's dual
17
 *          ported memory will be used and that it is configured
18
 *          correctly.  The node owning the memory CANNOT access it
19
 *          using a local address.  The "if" insures that the MASTER
20
 *          node uses a local address to access the dual-ported memory.
21
 *
22
 *          The interprocessor interrupt used on the CVME961 is generated
23
 *          by the VIC068.   The ICMS capablities of the VIC068 are used
24
 *          to generate interprocessor interrupts for up to eight nodes.
25
 *
26
 *           The following table illustrates the configuration limitations:
27
 *
28
 *                                   BUS     MAX
29
 *                          MODE    ENDIAN  NODES
30
 *                        ========= ====== =======
31
 *                         POLLED   LITTLE  2+
32
 *                        INTERRUPT LITTLE  2-8
33
 *
34
 *  COPYRIGHT (c) 1989-1997.
35
 *  On-Line Applications Research Corporation (OAR).
36
 *  Copyright assigned to U.S. Government, 1994.
37
 *
38
 *  The license and distribution terms for this file may in
39
 *  the file LICENSE in this distribution or at
40
 *  http://www.OARcorp.com/rtems/license.html.
41
 *
42
 *  $Id: getcfg.c,v 1.2 2001-09-27 11:59:59 chris Exp $
43
 */
44
 
45
#include <rtems.h>
46
#include "shm_driver.h"
47
 
48
#define USE_ONBOARD_RAM 0             /* use onboard (1) or VME RAM   */
49
                                      /*   for SHM communications     */
50
 
51
#define INTERRUPT 1                   /* CVME961 target supports both */
52
#define POLLING   0                   /* polling and interrupt modes  */
53
 
54
 
55
shm_config_table BSP_shm_cfgtbl;
56
 
57
void Shm_Get_configuration(
58
  rtems_unsigned32   localnode,
59
  shm_config_table **shmcfg
60
)
61
{
62
#if ( USE_ONBOARD_RAM == 1 )
63
   if ( Shm_RTEMS_MP_Configuration->node == MASTER )
64
     BSP_shm_cfgtbl.base   = (rtems_unsigned32 *)0x00300000;
65
   else
66
     BSP_shm_cfgtbl.base   = (rtems_unsigned32 *)0x10300000;
67
#else
68
   BSP_shm_cfgtbl.base     = (rtems_unsigned32 *)0x20000000;
69
#endif
70
 
71
   BSP_shm_cfgtbl.length       = 1 * MEGABYTE;
72
   BSP_shm_cfgtbl.format       = SHM_LITTLE;
73
 
74
   BSP_shm_cfgtbl.cause_intr   = Shm_Cause_interrupt;
75
 
76
#ifdef NEUTRAL_BIG
77
   BSP_shm_cfgtbl.convert      = (void *)CPU_swap_u32;
78
#else
79
   BSP_shm_cfgtbl.convert      = NULL_CONVERT;
80
#endif
81
 
82
#if (POLLING==1)
83
   BSP_shm_cfgtbl.poll_intr    = POLLED_MODE;
84
   BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT;
85
   BSP_shm_cfgtbl.Intr.value   = NO_INTERRUPT;
86
   BSP_shm_cfgtbl.Intr.length  = NO_INTERRUPT;
87
#else
88
   BSP_shm_cfgtbl.poll_intr    = INTR_MODE;
89
   BSP_shm_cfgtbl.Intr.address =
90
        (rtems_unsigned32 *) (0xffff0021|((localnode-1) << 12));
91
                                                          /* use ICMS0 */
92
   BSP_shm_cfgtbl.Intr.value   = 1;
93
   BSP_shm_cfgtbl.Intr.length  = BYTE;
94
#endif
95
 
96
   *shmcfg = &BSP_shm_cfgtbl;
97
 
98
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.