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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i960/] [rxgen960/] [shmsupp/] [mpisr.c] - Blame information for rev 30

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1 30 unneback
/*
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 *  NOTE: This routine is not used when in polling mode.  Either
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 *        this routine OR Shm_clockisr is used in a particular system.
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 *
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 *        There must be sufficient time after the IACK (read at
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 *        0xb600000x) for the VIC068 to clear the interrupt request
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 *        before the interrupt request is cleared from IPND (sf0).
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 *
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 *  COPYRIGHT (c) 1989-1997.
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 *  On-Line Applications Research Corporation (OAR).
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 *  Copyright assigned to U.S. Government, 1994.
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 *
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 *  The license and distribution terms for this file may in
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 *  the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: mpisr.c,v 1.2 2001-09-27 11:59:59 chris Exp $
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 */
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#include <rtems.h>
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#include <bsp.h>
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#include "shm_driver.h"
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rtems_isr Shm_isr_rxgen960(
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  rtems_vector_number vector
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)
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{
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  rtems_unsigned32 vic_vector;
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  /* enable_tracing(); */
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  vic_vector = (*(volatile rtems_unsigned8 *)0xb6000007);
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                                           /* reset intr by reading */
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                                           /*   vector at IPL=3 */
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  Shm_Interrupt_count += 1;
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  rtems_multiprocessing_announce();
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  (*(volatile rtems_unsigned8 *)0xa000005f) = 0; /* clear ICMS0 */
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  i960_clear_intr( 6 );
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}
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/*  void _Shm_setvec( )
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 *
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 *  This driver routine sets the SHM interrupt vector to point to the
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 *  driver's SHM interrupt service routine.
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 *
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 *  NOTE: See pp. 21-22, 36-39 of the CVME961 Manual for more info.
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 *
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 *  Input parameters:  NONE
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 *
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 *  Output parameters: NONE
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 */
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void Shm_setvec()
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{
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  rtems_unsigned32 isrlevel;
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  rtems_interrupt_disable( isrlevel );
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                                        /* set SQSIO4 CTL REG for */
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                                        /*   VME slave address */
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    (*(rtems_unsigned8 *)0xc00000b0) =
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      (Shm_RTEMS_MP_Configuration->node - 1) | 0x10;
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    set_vector( Shm_isr_rxgen960, 6, 1 );
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                                        /* set ICMS Bector Base Register */
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    (*(rtems_unsigned8 *)0xa0000053) = 0x60;  /* XINT6 vector is 0x62 */
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                                        /* set  ICMS Intr Control Reg */
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    (*(rtems_unsigned8 *)0xa0000047) = 0xeb;  /* ICMS0 enabled, IPL=0 */
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    (*(rtems_unsigned8 *)0xa000005f) = 0;     /* clear ICMS0 */
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  rtems_interrupt_enable( isrlevel );
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}

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