OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i960/] [rxgen960/] [shmsupp/] [mpisr.c] - Blame information for rev 814

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  NOTE: This routine is not used when in polling mode.  Either
3
 *        this routine OR Shm_clockisr is used in a particular system.
4
 *
5
 *        There must be sufficient time after the IACK (read at
6
 *        0xb600000x) for the VIC068 to clear the interrupt request
7
 *        before the interrupt request is cleared from IPND (sf0).
8
 *
9
 *  COPYRIGHT (c) 1989-1997.
10
 *  On-Line Applications Research Corporation (OAR).
11
 *  Copyright assigned to U.S. Government, 1994.
12
 *
13
 *  The license and distribution terms for this file may in
14
 *  the file LICENSE in this distribution or at
15
 *  http://www.OARcorp.com/rtems/license.html.
16
 *
17
 *  $Id: mpisr.c,v 1.2 2001-09-27 11:59:59 chris Exp $
18
 */
19
 
20
#include <rtems.h>
21
#include <bsp.h>
22
#include "shm_driver.h"
23
 
24
rtems_isr Shm_isr_rxgen960(
25
  rtems_vector_number vector
26
)
27
{
28
  rtems_unsigned32 vic_vector;
29
 
30
  /* enable_tracing(); */
31
  vic_vector = (*(volatile rtems_unsigned8 *)0xb6000007);
32
                                           /* reset intr by reading */
33
                                           /*   vector at IPL=3 */
34
  Shm_Interrupt_count += 1;
35
  rtems_multiprocessing_announce();
36
  (*(volatile rtems_unsigned8 *)0xa000005f) = 0; /* clear ICMS0 */
37
  i960_clear_intr( 6 );
38
 
39
}
40
 
41
/*  void _Shm_setvec( )
42
 *
43
 *  This driver routine sets the SHM interrupt vector to point to the
44
 *  driver's SHM interrupt service routine.
45
 *
46
 *  NOTE: See pp. 21-22, 36-39 of the CVME961 Manual for more info.
47
 *
48
 *  Input parameters:  NONE
49
 *
50
 *  Output parameters: NONE
51
 */
52
 
53
void Shm_setvec()
54
{
55
  rtems_unsigned32 isrlevel;
56
 
57
  rtems_interrupt_disable( isrlevel );
58
                                        /* set SQSIO4 CTL REG for */
59
                                        /*   VME slave address */
60
    (*(rtems_unsigned8 *)0xc00000b0) =
61
      (Shm_RTEMS_MP_Configuration->node - 1) | 0x10;
62
    set_vector( Shm_isr_rxgen960, 6, 1 );
63
                                        /* set ICMS Bector Base Register */
64
    (*(rtems_unsigned8 *)0xa0000053) = 0x60;  /* XINT6 vector is 0x62 */
65
                                        /* set  ICMS Intr Control Reg */
66
    (*(rtems_unsigned8 *)0xa0000047) = 0xeb;  /* ICMS0 enabled, IPL=0 */
67
    (*(rtems_unsigned8 *)0xa000005f) = 0;     /* clear ICMS0 */
68
  rtems_interrupt_enable( isrlevel );
69
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.