OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [i960/] [rxgen960/] [timer/] [timerisr.S] - Blame information for rev 562

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  timer_isr()
2
 *
3
 *  This routine initializes the Z8536 timer on the SQSIO4 SQUALL
4
 *  board for the CVME961 board.  The timer is setup to provide a
5
 *  tick every 0x10000 / 2 milliseconds.  This is used to time
6
 *  executing code.
7
 *
8
 *  Input parameters:  NONE
9
 *
10
 *  Output parameters:  NONE
11
 *
12
 *  COPYRIGHT (c) 1989-1997.
13
 *  On-Line Applications Research Corporation (OAR).
14
 *  Copyright assigned to U.S. Government, 1994.
15
 *
16
 *  The license and distribution terms for this file may in
17
 *  the file LICENSE in this distribution or at
18
 *  http://www.OARcorp.com/rtems/license.html.
19
 *
20
 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:00 chris Exp $
21
 */
22
 
23
#include "asm.h"
24
 
25
.set PORT_A,     0xc00000a8                 # port A
26
.set PORT_B,     0xc00000a4                 # port B
27
.set PORT_C,     0xc00000a0                 # port C
28
.set CTL_PORT,   0xc00000ac                 # control port
29
 
30
.set T1CSR,      0x0a                       # T1 command/status reg
31
.set RELOAD,     0x24                       # clr IP & IUS,allow countdown
32
 
33
/*
34
 * Duplicating this symbol is stupid but eliminates
35
 * toolset variation problems.
36
 */
37
        PUBLIC(timerisr)
38
        PUBLIC(_timerisr)
39
SYM (timerisr):
40
SYM (_timerisr):
41
        #ldconst   1,r4
42
        #modpc     0,r4,r4               # enable tracing
43
 
44
        ld      _Ttimer_val,r6           # r6 = test timer
45
 
46
        ldconst T1CSR,r4                 # r4 = T1 control status reg
47
        stob    r4,CTL_PORT              # select T1CSR
48
        ldconst RELOAD,r5                # r5 = reset value
49
        stob    r5,CTL_PORT              # reset countdown
50
        addo    1,r6,r6
51
        st      r6,_Ttimer_val           # increment test timer
52
loop_til_cleared:
53
        /* clrbit 4,sf0,sf0 XXX JRS */
54
        /* bbs    4,sf0,loop_til_cleared XXX JRS */
55
leaf:   ret
56
 
57
        .leafproc _flush_reg, flush_reg.lf
58
        .globl    _flush_reg, flush_reg.lf
59
_flush_reg:
60
        lda     leaf,g14                 # g14 = exit address
61
flush_reg.lf:
62
        flushreg
63
        mov     g14,g0                   # g0 = exit address
64
        ldconst 0,g14                    # set g14 for non-leaf
65
        bx      (g0)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.