OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [dmv152/] [include/] [bsp.h] - Blame information for rev 814

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  bsp.h
2
 *
3
 *  This include file contains all DMV152 board IO definitions.
4
 *
5
 *  COPYRIGHT (c) 1989-1999.
6
 *  On-Line Applications Research Corporation (OAR).
7
 *
8
 *  The license and distribution terms for this file may be
9
 *  found in the file LICENSE in this distribution or at
10
 *  http://www.OARcorp.com/rtems/license.html.
11
 *
12
 *  $Id: bsp.h,v 1.2 2001-09-27 12:00:00 chris Exp $
13
 */
14
 
15
#ifndef __DMV152_h
16
#define __DMV152_h
17
 
18
#ifdef __cplusplus
19
extern "C" {
20
#endif
21
 
22
#include <rtems.h>
23
#include <console.h>
24
#include <clockdrv.h>
25
#include <iosupp.h>
26
#include <vmeintr.h>
27
#include <zilog/z8530.h>
28
#include <zilog/z8536.h>
29
 
30
/*
31
 *  confdefs.h overrides for this BSP:
32
 *   - number of termios serial ports (defaults to 1)
33
 *   - Interrupt stack space is not minimum if defined.
34
 */
35
 
36
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
37
#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
38
 
39
/*
40
 *  confdefs.h overrides for this BSP:
41
 *   - termios serial ports (defaults to 1)
42
 *   - Interrupt stack space is not minimum if defined.
43
 */
44
 
45
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
46
/* #define CONFIGURE_INTERRUPT_STACK_MEMORY  (TBD * 1024) */
47
 
48
/*
49
 *  Define the time limits for RTEMS Test Suite test durations.
50
 *  Long test and short test duration limits are provided.  These
51
 *  values are in seconds and need to be converted to ticks for the
52
 *  application.
53
 *
54
 */
55
 
56
#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
57
#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
58
 
59
/*
60
 *  Define the interrupt mechanism for Time Test 27
61
 */
62
 
63
/* use a VMEbus interrupt */
64
 
65
#define MUST_WAIT_FOR_INTERRUPT 1
66
 
67
#define Install_tm27_vector( handler ) \
68
  { \
69
    set_vector( (handler), 0x50, 1 );  \
70
    (*(volatile rtems_unsigned32 *)0x0d800024) = 0x50; /* set IVECT reg */ \
71
    (*(volatile rtems_unsigned8  *)0x0d00000c) = 0x40; /* set VIE reg */ \
72
  }
73
 
74
#define Cause_tm27_intr()  \
75
  (*(volatile rtems_unsigned8 *)0x0d000003) = 0x0f  /* set VINT */
76
 
77
#define Clear_tm27_intr()  /* no operation necessary */
78
 
79
#define Lower_tm27_intr()
80
 
81
/*
82
 *  Simple spin delay in microsecond units for device drivers.
83
 *  This is very dependent on the clock speed of the target.
84
 */
85
 
86
#define delay( microseconds ) \
87
  { register rtems_unsigned32 _delay=(microseconds); \
88
    register rtems_unsigned32 _tmp=123; \
89
    asm volatile( "0: \
90
                     nbcd      %0 ; \
91
                     nbcd      %0 ; \
92
                     dbf       %1,0b" \
93
                  : "=d" (_tmp), "=d" (_delay) \
94
                  : "0"  (_tmp), "1"  (_delay) ); \
95
  }
96
 
97
/* macros */
98
 
99
#undef Z8x36_STATE0
100
#undef Z8x36_WRITE
101
#undef Z8x36_READ
102
 
103
#define Z8x36_STATE0 ( z8536 ) \
104
  { char *garbage; \
105
    (garbage) = *(VOL8(z8536+0x7)) \
106
  }
107
 
108
#define Z8x36_WRITE( z8536, reg, data ) \
109
   *(VOL8(z8536+0x7)) = (reg); \
110
   *(VOL8(z8536+0x7)) = (data)
111
 
112
#define Z8x36_READ( z8536, reg, data ) \
113
   *(VOL8(z8536+0x7)) = (reg); \
114
   (data) = *(VOL8(z8536+0x7))
115
 
116
/*
117
 *  ACC Register Addresses
118
 */
119
 
120
#define ACC_BASE    0x0D000000
121
 
122
#define ACC_STAT0   ((volatile rtems_unsigned8 *) (ACC_BASE + 0x00))
123
#define ACC_STAT1   ((volatile rtems_unsigned8 *) (ACC_BASE + 0x01))
124
#define ACC_GENCTL  ((volatile rtems_unsigned8 *) (ACC_BASE + 0x02))
125
#define ACC_VINT    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x03))
126
#define ACC_VREQ    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x04))
127
#define ACC_VARB    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x05))
128
#define ACC_ID      ((volatile rtems_unsigned8 *) (ACC_BASE + 0x06))
129
#define ACC_CTL2    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x07))
130
#define ACC_7IS     ((volatile rtems_unsigned8 *) (ACC_BASE + 0x08))
131
#define ACC_LIS     ((volatile rtems_unsigned8 *) (ACC_BASE + 0x09))
132
#define ACC_7IE     ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0A))
133
#define ACC_LIE     ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0B))
134
#define ACC_VIE     ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0C))
135
#define ACC_IC10    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0D))
136
#define ACC_IC32    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0E))
137
#define ACC_IC54    ((volatile rtems_unsigned8 *) (ACC_BASE + 0x0F))
138
 
139
/* constants */
140
 
141
#define TIMER 0x0c000000
142
#define TIMER_VECTOR 0x4D
143
 
144
#define CONSOLE_CONTROL_A  0x0C800005
145
#define CONSOLE_DATA_A     0x0C800007
146
#define CONSOLE_CONTROL_B  0x0C800001
147
#define CONSOLE_DATA_B     0x0C800003
148
 
149
/* Structures */
150
 
151
   /* none */
152
 
153
/* miscellaneous stuff assumed to exist */
154
 
155
extern rtems_configuration_table BSP_Configuration;
156
 
157
extern m68k_isr_entry M68Kvec[];   /* vector table address */
158
 
159
/*
160
 *  Device Driver Table Entries
161
 */
162
 
163
/*
164
 * NOTE: Use the standard Console driver entry
165
 */
166
 
167
/*
168
 * NOTE: Use the standard Clock driver entry
169
 */
170
 
171
/* functions */
172
 
173
void bsp_cleanup( void );
174
 
175
m68k_isr_entry set_vector(
176
  rtems_isr_entry     handler,
177
  rtems_vector_number vector,
178
  int                 type
179
);
180
 
181
#ifdef __cplusplus
182
}
183
#endif
184
 
185
#endif
186
/* end of include file */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.