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unneback |
/* entry.s
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*
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* This file contains the entry point for the application.
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* The name of this entry point is compiler dependent.
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* It jumps to the BSP which is responsible for performing
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* all initialization.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: start.S,v 1.2 2001-09-27 12:00:05 chris Exp $
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*/
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#include "asm.h"
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.set BAR, 0xF2 | Base Address Register location
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.set SCR, 0xF4 | System Control Register location
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.set BAR_VAL, 0x0f7f | BAR value
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.set SCR_VAL, 0x00080f00 | SCR value
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.set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN).
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.set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address
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.set oSYSRAM, 0x000 | 576 bytes of internal system RAM
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.set oGIMR, 0x812
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.set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg
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.set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg
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.set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg
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.set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg
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.set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg
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.set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg
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.set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg
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.set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg
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.set tmpSRAM_BASE, 0x400000 | start of temporary SRAM
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.set FLASH_BASE, 0xc00000 | start of FLASH''s normal location
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BEGIN_CODE
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PUBLIC (M68Kvec) | Vector Table
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SYM (M68Kvec): | standard location for vectors
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V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP
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V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC
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V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error
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V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error
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.space 240 | reserve space for reset of vectors
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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SYM (lowintstack):
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.space 4092 | reserve for interrupt stack
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SYM (hiintstack):
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.space 4 | end of interrupt stack
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#endif
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PUBLIC (start) | Default entry point for GNU
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SYM (start):
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move.w #0x2700,sr | Disable all interrupts
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move.w #BAR_VAL,BAR | Set Base Address Register
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move.l #SCR_VAL,SCR | Set System Control Register
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lea BaseAddr,a5
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move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register
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| Set up chip select registers for the remapping process.
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| 0 X x x x x
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| 0 000 0 0-- - --- ---- ---- ----
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| x xxx x xxx x xx
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move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH)
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move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS
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| X x x x x x
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| 0 100 0 0-- - --- ---- ---- ----
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| x xxx x xxx x xx
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move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM)
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move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS
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| Copy the initial boot FLASH area to the temporary SRAM location.
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moveq #0,d0
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movea.l d0,a0 | a0 -> start of FLASH
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lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM
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| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy
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moveq #127,d0
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cpy_flash: move.l (a0)+,(a1)+ | copy
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subq.l #1,d0
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bne cpy_flash
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| Copy remap code to 68302''s internal system RAM.
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movea.w #begRemap-V___ISSP,a0 | a0 -> remap code
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lea a5@(oSYSRAM),a1 | a1 -> internal system RAM
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| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy
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moveq #11,d0
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cpy_remap: move.w (a0)+,(a1)+ | copy
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dbra d0,cpy_remap
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| Jump to the remap code in the 68302''s internal system RAM.
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jmp a5@(oSYSRAM) | (effectively a jmp begRemap)
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| This remap code, when executed from the 68302''s internal system RAM
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| will 1) remap CS1 so that SRAM is at 0
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| 2) remap CS0 so that FLASH is at FLASH_BASE
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| and 3) jump to executable code in the remapped FLASH.
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begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM)
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move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH)
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lea FLASH_BASE,a0
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jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH
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endRemap:
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| Now set up the remaining chip select registers.
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| 4 0 x x x x
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| 1 000 1 111 0 000 0--- ---- ----
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| x xxx x xxx x xx
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move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM)
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move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS
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| 8 X x x x x
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| 1 000 0 0-- - --- ---- ---- ----
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| x xxx x xxx x xx
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move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO)
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move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS
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endPreBoot:
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move.b #0x30,0x800001 | set status LED amber
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.set oPIOB_Ctrl, 0x824
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.set oPIOB_DDR, 0x826
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.set oPIOB_Data, 0x828
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.set oPIOA_Ctrl, 0x81e
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.set oPIOA_DDR, 0x820
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.set oPIOA_Data, 0x822
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move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors.
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move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output.
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move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated
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| peripheral pins.
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move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors.
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move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output.
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move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated
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| peripheral pins.
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| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4
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| are not set because they are the 68302''s BAR and SCR.
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movea.w #0x010,a0
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moveq #(0x0f0-0x010)/4-1,d0
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move.l #Bad,d1
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cpy_Bad: move.l d1,(a0)+
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dbra d0,cpy_Bad
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.set vbase, 0x0200
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lea vbase,a0
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moveq #31,d0
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cpy_Bad1: move.l d1,(a0)+
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dbra d0,cpy_Bad1
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| Fill in special locations to configure OS
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move.l #Bad,0x008 | Bus Error
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move.l #Bad,0x00c | Address Error
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move.l #Bad,0x024 | Trace
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| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call
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| move.l #_cnsl_isr,vbase+0x028 | SCC2
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move.l #timerisr,vbase+0x018 | Timer ISR
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| zero out uninitialized data area
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zerobss:
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moveal # SYM (_clear_end),a0 | find end of .bss
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moveal # SYM (_clear_start),a1 | find beginning of .bss
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moveq #0,d0
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loop: movel d0,a1@+ | to zero out uninitialized
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cmpal a0,a1
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jlt loop | loop until _clear_end reached
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movel d0, SYM (_stack_init) | Set Stack pointer
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movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!!
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movel d0,a7 | set master stack pointer
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movel d0,a6 | set base pointer
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/*
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* RTEMS should maintain a separate interrupt stack on CPUs
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* without one in hardware. This is currently not supported
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* on versions of the m68k without a HW intr stack.
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*/
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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lea SYM (hiintstack),a0 | a0 = high end of intr stack
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movec a0,isp | set interrupt stack
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#endif
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move.l #0,a7@- | environp
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move.l #0,a7@- | argv
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move.l #0,a7@- | argc
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jsr SYM (boot_card)
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nop
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Bad: bra Bad
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nop
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END_CODE
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BEGIN_DATA
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PUBLIC (start_frame)
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SYM (start_frame):
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.space 4,0
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PUBLIC (stack_start)
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SYM (stack_start):
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.space 4,0
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END_DATA
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BEGIN_BSS
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PUBLIC (environ)
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.align 2
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SYM (environ):
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.long 0
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PUBLIC (heap_size)
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.set SYM (heap_size),0x2000
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PUBLIC (stack_size)
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.set SYM (stack_size),0x1000
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END_DATA
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END
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