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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [gen68340/] [include/] [m68340.inc] - Blame information for rev 173

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1 30 unneback 
/*----------------------------------------------------------------------------
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* file name: M68340.INC                                 JC RAHUEL CNET/DSM/TAM/CAT
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*
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* MC68340 BCC  Board Support Package
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*
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* date: 1/12/1993
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*
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* Copyright 1989, Ready Systems FRANCE
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*
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* Supports: VRTX32 and RTscope
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*
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* Related Board: MOTOROLA BCC M68340
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*
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* Description:  EQUATES FOR 68340 DEVICES
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*
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* Changes:
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*       - Geoffroy Montel (g_montel@yahoo.com) :
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*         changed EQU syntax for GNU as
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*
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*----------------------------------------------------------------------------*/
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/************************************************
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 * ATTENTION: must match defs. in C header file *
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 ************************************************/
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/* -- SIM equates --    system integration module */
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.equ BASE_REG, 0x3FF00
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.equ BASE_SIM, 0xEFFFF000
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.equ SIM_MCR, 0x000     /* module configuration register */
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.equ SIM_SYNCR, 0x004   /* clock synthesizer control register */
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.equ SIM_AVR, 0x006     /* autovector register */
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.equ SIM_RSR, 0x007     /* reset status register */
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/* -- Port A -- */
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.equ SIM_PORTA, 0x011   /* port A data */
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.equ SIM_DDRA, 0x013    /* port A direction data */
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.equ SIM_PPRA1, 0x015   /* Port A pin assignement 1 */
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.equ SIM_PPRA2, 0x017   /* Port A pin assignement 2 */
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/* -- Port B -- */
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.equ SIM_PORTB, 0x019   /* port B data */
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.equ SIM_PORTB1, 0x01B  /* port B data auxiliary */
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.equ SIM_DDRB, 0x01D    /* port B direction data */
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.equ SIM_PPRB, 0x01F    /* Port B pin assignement */
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.equ SIM_SWIV, 0x020    /* SW interrupt vector */
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.equ SIM_SYPCR, 0x021   /* System protection control register */
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.equ SIM_PICR, 0x022    /* Periodic interrupt control register */
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.equ SIM_PITR, 0x024    /* Periodic interrupt timing register */
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.equ SIM_SWSR, 0x027    /* Sofware service */
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/* -- Chip select -- */
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.equ SIM_MASKH0, 0x040  /* mask register CS0 */
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.equ SIM_MASKL0, 0x042  /* mask register CS0 */
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.equ SIM_ADDRH0, 0x044  /* base address CS0 */
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.equ SIM_ADDRL0, 0x046  /* base address CS0 */
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.equ SIM_MASKH1, 0x048  /* mask register CS1 */
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.equ SIM_MASKL1, 0x04A  /* mask register CS1 */
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.equ SIM_ADDRH1, 0x04C  /* base address CS1 */
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.equ SIM_ADDRL1, 0x04E  /* base address CS1 */
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.equ SIM_MASKH2, 0x050  /* mask register CS2 */
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.equ SIM_MASKL2, 0x052  /* mask register CS2 */
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.equ SIM_ADDRH2, 0x054  /* base address CS2 */
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.equ SIM_ADDRL2, 0x056  /* base address CS2 */
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.equ SIM_MASKH3, 0x058  /* mask register CS3 */
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.equ SIM_MASKL3, 0x05A  /* mask register CS3 */
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.equ SIM_ADDRH3, 0x05C  /* base address CS3 */
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.equ SIM_ADDRL3, 0x05E  /* base address CS3 */
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/* -- TIMERS  equates -- */
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/* __ TIMER 0 */
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.equ TIM_MCR0, 0x600    /* Module configuration register */
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.equ TIM_IR0, 0x604     /* interrupt register */
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.equ TIM_CR0, 0x606     /* controle register */
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.equ TIM_SR0, 0x608     /* Status/prescaler register */
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.equ TIM_CNTR0, 0x60A   /* counter register */
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.equ TIM_PREL10, 0x60C  /* Preload register 1 */
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.equ TIM_PREL20, 0x60E  /* Preload register 2 */
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.equ TIM_COM0, 0x610    /* Compare register */
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/* __ TIMER 1 */
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.equ TIM_MCR1, 0x640    /* Module configuration register */
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.equ TIM_IR1, 0x644     /* interrupt register */
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.equ TIM_CR1, 0x646     /* controle register */
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.equ TIM_SR1, 0x648     /* Status/prescaler register */
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.equ TIM_CNTR1, 0x64A   /* counter register */
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.equ TIM_PREL11, 0x64C  /* Preload register 1 */
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.equ TIM_PREL21, 0x64E  /* Preload register 2 */
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.equ TIM_COM1, 0x650    /* Compare register */
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/* -- U.A.R.T.  equates -- */
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.equ UA_MCRH, 0x700     /* module configuration register */
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.equ UA_MCRL, 0x701     /* module configuration register */
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.equ UA_ILR, 0x704      /* Interrupt level */
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.equ UA_IVR, 0x705      /* Interrupt vector */
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.equ UA_MR1A, 0x710     /* Mode register 1 A */
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.equ UA_MR2A, 0x720     /* Mode register 2 A*/
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.equ UA_CSRA, 0x711     /* Clock_select register A */
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.equ UA_SRA, 0x711      /* status register A */
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.equ UA_CRA, 0x712      /* command register A */
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.equ UA_RBA, 0x713      /* receive buffer A */
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.equ UA_TBA, 0x713      /* transmit buffer A */
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.equ UA_IPCR, 0x714     /* input port change register */
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.equ UA_ACR, 0x714      /* auxiliary control register */
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.equ UA_ISR, 0x715      /* interrupt status register */
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.equ UA_IER, 0x715      /* interrupt enable register */
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.equ UA_MR1B, 0x718     /* Mode register 1 B */
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.equ UA_MR2B, 0x721     /* Mode register  2 B */
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.equ UA_CSRB, 0x719     /* Clock_select register B */
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.equ UA_SRB, 0x719      /* status register B */
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.equ UA_CRB, 0x71A      /* command register A */
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.equ UA_RBB, 0x71B      /* receive buffer A */
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.equ UA_TBB, 0x71B      /* transmit buffer A */
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.equ UA_IP, 0x71D       /* Input port register */
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.equ UA_OPCR, 0x71D     /* output port control register */
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.equ UA_OPS, 0x71E      /* output port bit set */
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.equ UA_OPR, 0x71F      /* output port bit reset */
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.equ TX_A_EN, 0x01      /* Tx A irq enable */
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.equ TX_B_EN, 0x10      /* Tx B irq enable */
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.equ TX_A_DIS, 0xFE     /* Tx A irq enable */
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.equ TX_B_DIS, 0xEF     /* Tx B irq enable */
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.equ TX_AB_DIS, 0x22
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/* -- DMA equates -- */
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.equ DMA_MCR0, 0x780    /* module configuration register */
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.equ DMA_IR0, 0x784     /* Interrupt register */
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.equ DMA_CCR0, 0x788    /* Channel control register */
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.equ DMA_CSR0, 0x78A    /* Channel status register */
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.equ DMA_FCR0, 0x78B    /* Function code register */
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.equ DMA_SARH0, 0x78C   /* Source adresse register */
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.equ DMA_SARL0, 0x78E   /* Source adresse register */
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.equ DMA_DARH0, 0x790   /* destination adresse register */
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.equ DMA_DARL0, 0x792   /* destination adresse register */
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.equ DMA_BTCH0, 0x794   /* byte transfer register */
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.equ DMA_BTCL0, 0x796   /* byte transfer register */
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.equ DMA_MCR1, 0x7A0    /* module configuration register */
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.equ DMA_IR1, 0x7A4     /* Interrupt register */
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.equ DMA_CCR1, 0x7A8    /* Channel control register */
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.equ DMA_CSR1, 0x7AA    /* Channel status register */
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.equ DMA_FCR1, 0x7AB    /* Function code register */
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.equ DMA_SARH1, 0x7AC   /* Source adresse register */
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.equ DMA_SARL1, 0x7AE   /* Source adresse register */
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.equ DMA_DARH1, 0x7B0   /* destination adresse register */
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.equ DMA_DARL1, 0x7B2   /* destination adresse register */
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.equ DMA_BTCH1, 0x7B4   /* byte transfer register */
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.equ DMA_BTCL1, 0x7B6   /* byte transfer register */

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