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/*----------------------------------------------------------------------------
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* file name: M68349.INC P. CADIC CNET/DSM/TAM/CAT
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*
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* MC68349 BCC Board Support Package
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*
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* date: 31/07/97
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*
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* Description: EQUATES FOR 68349 DEVICES
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*
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* Modifications:
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* - adapted for GNU CC by G.Montel 26/05/98
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*----------------------------------------------------------------------------*/
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| -- SIM equates --
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.equ BASE_REG, 0x3FF00
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| 17 |
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.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK
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| 19 |
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.equ SIM_MCR, 0x000 | module configuration register
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| 20 |
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.equ SIM_IDR, 0x002 | processor identification register
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| 21 |
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.equ SIM_SYNCR, 0x004 | clock synthesizer control register
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| 22 |
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.equ SIM_AVR, 0x006 | autovector register
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| 23 |
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.equ SIM_RSR, 0x007 | reset status register
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| 24 |
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| 25 |
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| -- Port A
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.equ SIM_PORTA, 0x011 | port A data
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.equ SIM_DDRA, 0x013 | port A direction data
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.equ SIM_PPRA1, 0x015 | Port A pin assignement 1
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.equ SIM_PPRA2, 0x017 | Port A pin assignement 2
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| 31 |
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| -- Port B
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.equ SIM_PORTB, 0x019 | port B data
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.equ SIM_PORTB1, 0x01B | port B data auxiliary
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.equ SIM_DDRB, 0x01D | port B direction data
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.equ SIM_PPRB, 0x01F | Port B pin assignement
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| 37 |
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.equ SIM_SWIV, 0x020 | SW interrupt vector
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.equ SIM_SYPCR, 0x021 | System protection control register
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.equ SIM_PICR, 0x022 | Periodic interrupt control register
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.equ SIM_PITR, 0x024 | Periodic interrupt timing register
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| 41 |
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.equ SIM_SWSR, 0x027 | Sofware service
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| 42 |
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| 43 |
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| -- Chip select
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| 44 |
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.equ SIM_MASKH0, 0x040 | mask register CS0
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| 45 |
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.equ SIM_MASKL0, 0x042 | mask register CS0
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.equ SIM_ADDRH0, 0x044 | base address CS0
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.equ SIM_ADDRL0, 0x046 | base address CS0
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| 49 |
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.equ SIM_MASKH1, 0x048 | mask register CS1
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| 50 |
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.equ SIM_MASKL1, 0x04A | mask register CS1
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| 51 |
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.equ SIM_ADDRH1, 0x04C | base address CS1
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.equ SIM_ADDRL1, 0x04E | base address CS1
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.equ SIM_MASKH2, 0x050 | mask register CS2
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.equ SIM_MASKL2, 0x052 | mask register CS2
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.equ SIM_ADDRH2, 0x054 | base address CS2
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.equ SIM_ADDRL2, 0x056 | base address CS2
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.equ SIM_MASKH3, 0x058 | mask register CS3
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.equ SIM_MASKL3, 0x05A | mask register CS3
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| 61 |
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.equ SIM_ADDRH3, 0x05C | base address CS3
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.equ SIM_ADDRL3, 0x05E | base address CS3
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| -- TIMERS equates --
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| __ TIMER 0
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.equ TIM_MCR0, 0x600 | Module configuration register
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.equ TIM_IR0, 0x604 | interrupt register
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.equ TIM_CR0, 0x606 | controle register
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.equ TIM_SR0, 0x608 | Status/prescaler register
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.equ TIM_CNTR0, 0x60A | counter register
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.equ TIM_PREL10, 0x60C | Preload register 1
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.equ TIM_PREL20, 0x60E | Preload register 2
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.equ TIM_COM0, 0x610 | Compare register
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| __ TIMER 1
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.equ TIM_MCR1, 0x640 | Module configuration register
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.equ TIM_IR1, 0x644 | interrupt register
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.equ TIM_CR1, 0x646 | controle register
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.equ TIM_SR1, 0x648 | Status/prescaler register
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.equ TIM_CNTR1, 0x64A | counter register
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.equ TIM_PREL11, 0x64C | Preload register 1
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.equ TIM_PREL21, 0x64E | Preload register 2
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.equ TIM_COM1, 0x650 | Compare register
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| -- U.A.R.T. equates --
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.equ UA_MCRH, 0x700 | module configuration register
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.equ UA_MCRL, 0x701 | module configuration register
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.equ UA_ILR, 0x704 | Interrupt level
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.equ UA_IVR, 0x705 | Interrupt vector
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.equ UA_MR1A, 0x710 | Mode register 1 A
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.equ UA_MR2A, 0x720 | Mode register 2 A
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.equ UA_CSRA, 0x711 | Clock_select regiter A
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.equ UA_SRA, 0x711 | status register A
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.equ UA_CRA, 0x712 | command register A
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.equ UA_RBA, 0x713 | receive buffer A
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.equ UA_TBA, 0x713 | transmit buffer A
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.equ UA_IPCR, 0x714 | input port change register
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.equ UA_ACR, 0x714 | auxiliary control register
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.equ UA_ISR, 0x715 | interrupt status register
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.equ UA_IER, 0x715 | interrupt enable register
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.equ UA_MR1B, 0x718 | Mode register 1 B
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.equ UA_MR2B, 0x721 | Mode register 2 B
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.equ UA_CSRB, 0x719 | Clock_select regiter B
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.equ UA_SRB, 0x719 | status register B
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.equ UA_CRB, 0x71A | command register A
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.equ UA_RBB, 0x71B | receive buffer A
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.equ UA_TBB, 0x71B | transmit buffer A
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.equ UA_IP, 0x71D | Input port register
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.equ UA_OPCR, 0x71D | output port control register
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| 118 |
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.equ UA_OPS, 0x71E | output port bit set
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| 119 |
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.equ UA_OPR, 0x71F | output port bit reset
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.equ TX_A_EN, 0x01 | Tx A irq enable
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.equ TX_B_EN, 0x10 | Tx B irq enable
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.equ TX_A_DIS, 0xFE | Tx A irq enable
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| 123 |
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.equ TX_B_DIS, 0xEF | Tx B irq enable
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.equ TX_AB_DIS, 0x22
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| -- DMA equates
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.equ DMA_MCR0, 0x780 | module configuration register
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.equ DMA_IR0, 0x784 | Interrupt register
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.equ DMA_CCR0, 0x788 | Channel control register
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.equ DMA_CSR0, 0x78A | Channel status register
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.equ DMA_FCR0, 0x78B | Function code register
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.equ DMA_SARH0, 0x78C | Source adresse register
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.equ DMA_SARL0, 0x78E | Source adresse register
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.equ DMA_DARH0, 0x790 | destination adresse register
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.equ DMA_DARL0, 0x792 | destination adresse register
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.equ DMA_BTCH0, 0x794 | byte transfer register
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| 138 |
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.equ DMA_BTCL0, 0x796 | byte transfer register
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| 140 |
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.equ DMA_MCR1, 0x7A0 | module configuration register
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| 141 |
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.equ DMA_IR1, 0x7A4 | Interrupt register
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| 142 |
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.equ DMA_CCR1, 0x7A8 | Channel control register
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| 143 |
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.equ DMA_CSR1, 0x7AA | Channel status register
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.equ DMA_FCR1, 0x7AB | Function code register
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.equ DMA_SARH1, 0x7AC | Source adresse register
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.equ DMA_SARL1, 0x7AE | Source adresse register
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.equ DMA_DARH1, 0x7B0 | destination adresse register
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.equ DMA_DARL1, 0x7B2 | destination adresse register
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| 149 |
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.equ DMA_BTCH1, 0x7B4 | byte transfer register
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| 150 |
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.equ DMA_BTCL1, 0x7B6 | byte transfer register
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| 152 |
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| -- cache equates
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| 153 |
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.equ CACHE_MCR, 0xFC0 | cache config reg. (long)
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| -- quad data memory module (QDMM) equates
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| 156 |
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.equ QDMM_MCR, 0xC00 | QDMM config reg (long)
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| 157 |
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.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long)
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| 158 |
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.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long)
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| 159 |
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.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long)
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| 160 |
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.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long)
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|-----------------------------------------------------
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| AST68349 internal registers
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|-----------------------------------------------------
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.equ EPLD_SPACE, 3 | "reserved user" space
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.equ CPU_SPACE, 7 | "CPU" space
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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| GLUE EPLD
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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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.equ GLUE_EPLD, 0xB0000000
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| configuration of /CS0 :
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| 179 |
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| 7 6 5 4 3 2 1 0
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| +---+---+---+---+---+---+---+---+
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| 181 |
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| |ena|val|wid| ws|b31|b30|b29|b28|
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| 182 |
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| +---+---+---+---+---+---+---+---+
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| 183 |
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| 184 |
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| b[31..28] : base address for decoding /CS[3..0]
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| the decoding is as follow :
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| 186 |
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| 187 |
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| +----------+------------+------+
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| | a[31..28] | a[27..26] | /CS |
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| 189 |
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| +-----------+-----------+------+
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| 190 |
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| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes
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| 191 |
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| | b[31..28] | 01 | /CS1 |
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| 192 |
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| | b[31..28] | 10 | /CS2 |
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| 193 |
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| | b[31..28] | 11 | /CS3 |
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| 194 |
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| +-----------------------+------+
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| 195 |
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| 196 |
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| after /RESET, /CS0 is validated for every cycle, until programmed
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| 198 |
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| ws : number of wait-states : 0 => 0 ws
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| 199 |
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| 1 => external /dsackx
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| 200 |
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| wid : width of chip-select : 0 => 16 bits
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| 201 |
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| 1 => 32 bits
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| 202 |
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| ena : enable chip-select : 0 => disabled
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| 203 |
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| 1 => enabled
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| 204 |
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| 205 |
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| val : automatic validation. set after reset
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| 206 |
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| cleared when /CS0 is configured
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| 208 |
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.equ REG_CS0, 0
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| 210 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 212 |
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| configuration of /CS1 to /CS3:
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| 213 |
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| 214 |
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| 7 6 5 4 3 2 1 0
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| 215 |
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| +---+---+---+---+---+---+---+---+
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| 216 |
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| |ena| x |wid| ws| x | x | x | x |
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| 217 |
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| +---+---+---+---+---+---+---+---+
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| 218 |
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| 219 |
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| ws : number of wait-states : 0 => 0 ws
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| 220 |
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| 1 => external /dsackx
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| 221 |
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| wid : width of chip-select : 0 => 16 bits
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| 222 |
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| 1 => 32 bits
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| 223 |
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| ena : enable chip-select : 0 => disabled
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| 224 |
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| 1 => enabled
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| 225 |
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.equ REG_CS1, 1
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| 226 |
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.equ REG_CS2, 2
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| 227 |
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.equ REG_CS3, 3
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| 228 |
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| 229 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 230 |
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| I2C register
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| 231 |
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| 232 |
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| 7 6 5 4 3 2 1 0
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| 233 |
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| +---+---+---+---+---+---+---+----+
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| 234 |
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| | x | x | x | x | x | x |clk|data|
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| 235 |
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| +---+---+---+---+---+---+---+----+
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| 236 |
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| bidirecionnal pin, open drain output.
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| 237 |
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| set bit to 1 to read external state of pin
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| 238 |
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| 239 |
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.equ REG_I2C, 4
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| 240 |
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| 241 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 242 |
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| PDCS register
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| 243 |
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| 244 |
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| 7 6 5 4 3 2 1 0
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| 245 |
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| +---+---+---+---+---+---+---+---+
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| 246 |
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| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
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| 247 |
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| +---+---+---+---+---+---+---+---+
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| 248 |
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| pd[5..1] : value read on the DRAM module
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| 249 |
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| S12, S11 and S14 : "user reserved" configuration switch
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| 250 |
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| 251 |
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.equ REG_PDCS, 5
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| 252 |
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| 253 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 254 |
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| timer1 register
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| 255 |
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| 256 |
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| 7 6 5 4 3 2 1 0
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| 257 |
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| +---+---+---+---+---+---+---+---+
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| 258 |
|
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| |ena| x | x | x | x | x | d1| d0|
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| 259 |
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| +---+---+---+---+---+---+---+---+
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| 260 |
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| 261 |
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| the timer clock is the 1000Hz clock of the ASTECC platform
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| 262 |
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| the timer is reloaded on each write to the register, or if the input
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| 263 |
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| TIN1 is set to 0.
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| 264 |
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| on overflow, the open drain output TOUT1 is set to 0
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| 265 |
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| the timer must be disabled to return TOUT1 to the inactive state
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| 266 |
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| 267 |
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.equ REG_TIMER1, 6
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| 268 |
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| 269 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 270 |
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| timer2 register
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| 271 |
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| 272 |
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| 7 6 5 4 3 2 1 0
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| 273 |
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| +---+---+---+---+---+---+---+---+
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| 274 |
|
|
| |ena| x | x | x | x | x | d1| d0|
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| 275 |
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| +---+---+---+---+---+---+---+---+
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| 276 |
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| the timer clock is the 1000Hz clock of the ASTECC platform
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| 277 |
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| the timer is reloaded on each write to the register, or if the input
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| 278 |
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| TIN2 is set to 0.
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| 279 |
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| on overflow, the open drain output TOUT2 is set to 0
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| 280 |
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| the timer must be disabled to return TOUT2 to the inactive state
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| 281 |
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| 282 |
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.equ REG_TIMER2, 7
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| 283 |
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| 284 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 285 |
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| baudrate generator register
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| 286 |
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| 287 |
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| 7 6 5 4 3 2 1 0
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| 288 |
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| +---+---+---+---+---+---+---+---+
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| 289 |
|
|
| | x | x | x | x | x | d2| d1| d0|
|
| 290 |
|
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| +---+---+---+---+---+---+---+---+
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| 291 |
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| 292 |
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| d[2..0] : divider of a 3.6864 Mhz clock
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| 293 |
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| 294 |
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| d[2..0] : 0 1 2 3 4 5 6 7
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| 295 |
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| divides by : 2 4 6 8 10 12 14 16
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| 296 |
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| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304
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| 297 |
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| baudrate : 115200 57600 38400 28800 x 19200 x 14400
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| 298 |
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| 299 |
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.equ REG_BAUDRATE, 8
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| 300 |
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| 301 |
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|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| 302 |
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| IO register
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| 303 |
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|
|
|
| 304 |
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| 7 6 5 4 3 2 1 0
|
| 305 |
|
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| +---+---+---+---+---+---+---+---+
|
| 306 |
|
|
| | x | x | x |io4|io3|io2|io1|io0|
|
| 307 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 308 |
|
|
|
|
| 309 |
|
|
| io[4..0] : data written to port
|
| 310 |
|
|
|
|
| 311 |
|
|
| maximum current load is about 5 mA per pin
|
| 312 |
|
|
|
|
| 313 |
|
|
.equ REG_IO, 9
|
| 314 |
|
|
|
| 315 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 316 |
|
|
| IO port
|
| 317 |
|
|
|
|
| 318 |
|
|
| 7 6 5 4 3 2 1 0
|
| 319 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 320 |
|
|
| | x | x | x |io4|io3|io2|io1|io0|
|
| 321 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 322 |
|
|
|
|
| 323 |
|
|
| io[4..0] : data read from port
|
| 324 |
|
|
|
|
| 325 |
|
|
.equ REG_IO_PORT, 10
|
| 326 |
|
|
|
| 327 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 328 |
|
|
| IO direction register
|
| 329 |
|
|
|
|
| 330 |
|
|
| 7 6 5 4 3 2 1 0
|
| 331 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 332 |
|
|
| | x | x | x | x | x |dr2|dr1|dr0|
|
| 333 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 334 |
|
|
|
|
| 335 |
|
|
| dr0 : 0 => io port 0 is configured as input (default after /RESET)
|
| 336 |
|
|
| 1 => io port 0 is configured as output
|
| 337 |
|
|
|
|
| 338 |
|
|
| dr1 : 0 => io port 1 is configured as input (default after /RESET)
|
| 339 |
|
|
| 1 => io port 1 is configured as output
|
| 340 |
|
|
|
|
| 341 |
|
|
| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
|
| 342 |
|
|
| 1 => io ports 2 to 4 are configured as output
|
| 343 |
|
|
|
|
| 344 |
|
|
.equ REG_DIR_IO, 11
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
| 350 |
|
|
| DRAM EPLD
|
| 351 |
|
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
| 352 |
|
|
|
| 353 |
|
|
.equ DRAM_EPLD, 0xA0000000
|
| 354 |
|
|
|
| 355 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 356 |
|
|
| number of wait-state for DRAM
|
| 357 |
|
|
|
|
| 358 |
|
|
| 7 6 5 4 3 2 1 0
|
| 359 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 360 |
|
|
| | x | x | x | x | x | x |ws1|ws0|
|
| 361 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 362 |
|
|
|
|
| 363 |
|
|
| ws[1..0] : 0 1 2 3
|
| 364 |
|
|
| wait states : 0 1 2 3
|
| 365 |
|
|
|
|
| 366 |
|
|
.equ REG_WS, 0
|
| 367 |
|
|
|
| 368 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 369 |
|
|
| configuration of refresh for DRAM
|
| 370 |
|
|
|
|
| 371 |
|
|
| 7 6 5 4 3 2 1 0
|
| 372 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 373 |
|
|
| |ena| x | x | x | x | x |rf1|rf0|
|
| 374 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 375 |
|
|
|
|
| 376 |
|
|
| rf[1..0] : 0 1 2 3
|
| 377 |
|
|
| refresh : 5µs 10µs 15µs 20µs
|
| 378 |
|
|
|
|
| 379 |
|
|
| ena == 0 : refresh disabled
|
| 380 |
|
|
| ena == 1 : refresh enabled
|
| 381 |
|
|
|
|
| 382 |
|
|
.equ REG_REFRESH, 1
|
| 383 |
|
|
|
| 384 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 385 |
|
|
| configuration of DRAM module size
|
| 386 |
|
|
|
|
| 387 |
|
|
| 7 6 5 4 3 2 1 0
|
| 388 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 389 |
|
|
| | x | x | x | x | x |sz2|sz1|sz0|
|
| 390 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 391 |
|
|
|
|
| 392 |
|
|
| sz[2..0] : 0 1 2 3 4 5 6 7
|
| 393 |
|
|
| size (Mbytes): 4 8 16 32 64 128 0 0
|
| 394 |
|
|
|
|
| 395 |
|
|
.equ REG_CONFIG, 2
|
| 396 |
|
|
|
| 397 |
|
|
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
| 398 |
|
|
| bus width of /CS0 during reset bw[1..0] : 0 1 2 3
|
| 399 |
|
|
| bus width : 32 16 8 ext. /dsackx
|
| 400 |
|
|
|
|
| 401 |
|
|
| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
|
| 402 |
|
|
| : sel == 1 => EPLD chip_selects (/CS[3..0])
|
| 403 |
|
|
|
|
| 404 |
|
|
| 7 6 5 4 3 2 1 0
|
| 405 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 406 |
|
|
| |bw1|bw0| x | x | x | x | x |sel|
|
| 407 |
|
|
| +---+---+---+---+---+---+---+---+
|
| 408 |
|
|
|
|
| 409 |
|
|
.equ REG_BUSWIDTH, 3
|
| 410 |
|
|
|
