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30 |
unneback |
/*
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* This file contains the entry point for the application.
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* The name of this entry point is compiler dependent.
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* It jumps to the BSP which is responsible for performing
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* all initialization.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Based on the `gen68360' board support package, and covered by the
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* original distribution terms.
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*
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* Geoffroy Montel
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* France Telecom - CNET/DSM/TAM/CAT
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* 4, rue du Clos Courtel
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* 35512 CESSON-SEVIGNE
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* FRANCE
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*
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* e-mail: g_montel@yahoo.com
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*
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* $Id: start.S,v 1.2 2001-09-27 12:00:07 chris Exp $
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*/
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#include "asm.h"
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#include
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#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */
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BEGIN_CODE
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/*
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* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
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*/
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Entry:
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.long SYM(m340)+1024 | 0: Initial SSP
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.long start | 1: Initial PC
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.long SYM(_uhoh) | 2: Bus error
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.long SYM(_uhoh) | 3: Address error
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.long SYM(_uhoh) | 4: Illegal instruction
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.long SYM(_uhoh) | 5: Zero division
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.long SYM(_uhoh) | 6: CHK, CHK2 instruction
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.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
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.long SYM(_uhoh) | 8: Privilege violation
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.long SYM(_uhoh) | 9: Trace
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.long SYM(_uhoh) | 10: Line 1010 emulator
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| 49 |
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.long SYM(_uhoh) | 11: Line 1111 emulator
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.long SYM(_uhoh) | 12: Hardware breakpoint
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.long SYM(_uhoh) | 13: Reserved for coprocessor violation
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.long SYM(_uhoh) | 14: Format error
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.long SYM(_uhoh) | 15: Uninitialized interrupt
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.long SYM(_uhoh) | 16: Unassigned, reserved
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| 55 |
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.long SYM(_uhoh) | 17:
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| 56 |
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.long SYM(_uhoh) | 18:
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| 57 |
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.long SYM(_uhoh) | 19:
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| 58 |
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.long SYM(_uhoh) | 20:
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| 59 |
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.long SYM(_uhoh) | 21:
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| 60 |
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.long SYM(_uhoh) | 22:
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| 61 |
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.long SYM(_uhoh) | 23:
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| 62 |
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.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
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| 63 |
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.long SYM(_uhoh) | 25: Level 1 interrupt autovector
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| 64 |
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.long SYM(_uhoh) | 26: Level 2 interrupt autovector
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.long SYM(_uhoh) | 27: Level 3 interrupt autovector
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| 66 |
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.long SYM(_uhoh) | 28: Level 4 interrupt autovector
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| 67 |
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.long SYM(_uhoh) | 29: Level 5 interrupt autovector
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| 68 |
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.long SYM(_uhoh) | 30: Level 6 interrupt autovector
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.long SYM(_uhoh) | 31: Level 7 interrupt autovector
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.long SYM(_uhoh) | 32: Trap instruction (0-15)
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.long SYM(_uhoh) | 33:
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| 72 |
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.long SYM(_uhoh) | 34:
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| 73 |
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.long SYM(_uhoh) | 35:
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| 74 |
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.long SYM(_uhoh) | 36:
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| 75 |
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.long SYM(_uhoh) | 37:
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| 76 |
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.long SYM(_uhoh) | 38:
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| 77 |
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.long SYM(_uhoh) | 39:
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| 78 |
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.long SYM(_uhoh) | 40:
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| 79 |
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.long SYM(_uhoh) | 41:
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| 80 |
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.long SYM(_uhoh) | 42:
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| 81 |
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.long SYM(_uhoh) | 43:
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| 82 |
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.long SYM(_uhoh) | 44:
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| 83 |
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.long SYM(_uhoh) | 45:
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| 84 |
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.long SYM(_uhoh) | 46:
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| 85 |
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.long SYM(_uhoh) | 47:
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| 86 |
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.long SYM(_uhoh) | 48: Reserved for coprocessor
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.long SYM(_uhoh) | 49:
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| 88 |
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.long SYM(_uhoh) | 50:
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| 89 |
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.long SYM(_uhoh) | 51:
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| 90 |
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.long SYM(_uhoh) | 52:
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| 91 |
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.long SYM(_uhoh) | 53:
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| 92 |
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.long SYM(_uhoh) | 54:
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| 93 |
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.long SYM(_uhoh) | 55:
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| 94 |
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.long SYM(_uhoh) | 56:
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| 95 |
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.long SYM(_uhoh) | 57:
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| 96 |
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.long SYM(_uhoh) | 58:
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.long SYM(_uhoh) | 59: Unassigned, reserved
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.long SYM(_uhoh) | 60:
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| 99 |
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.long SYM(_uhoh) | 61:
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| 100 |
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.long SYM(_uhoh) | 62:
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| 101 |
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.long SYM(_uhoh) | 63:
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.long SYM(_uhoh) | 64: User defined vectors (192)
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.long SYM(_uhoh) | 65:
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| 104 |
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.long SYM(_uhoh) | 66:
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| 105 |
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.long SYM(_uhoh) | 67:
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| 106 |
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.long SYM(_uhoh) | 68:
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| 107 |
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.long SYM(_uhoh) | 69:
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| 108 |
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.long SYM(_uhoh) | 70:
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| 109 |
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.long SYM(_uhoh) | 71:
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| 110 |
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.long SYM(_uhoh) | 72:
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| 111 |
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.long SYM(_uhoh) | 73:
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| 112 |
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.long SYM(_uhoh) | 74:
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| 113 |
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.long SYM(_uhoh) | 75:
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| 114 |
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.long SYM(_uhoh) | 76:
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| 115 |
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.long SYM(_uhoh) | 77:
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| 116 |
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.long SYM(_uhoh) | 78:
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| 117 |
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.long SYM(_uhoh) | 79:
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| 118 |
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.long SYM(_uhoh) | 80:
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| 119 |
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.long SYM(_uhoh) | 81:
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| 120 |
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.long SYM(_uhoh) | 82:
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| 121 |
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.long SYM(_uhoh) | 83:
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| 122 |
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.long SYM(_uhoh) | 84:
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| 123 |
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.long SYM(_uhoh) | 85:
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| 124 |
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.long SYM(_uhoh) | 86:
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| 125 |
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.long SYM(_uhoh) | 87:
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| 126 |
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.long SYM(_uhoh) | 88:
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| 127 |
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.long SYM(_uhoh) | 89:
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| 128 |
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.long SYM(_uhoh) | 90:
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| 129 |
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.long SYM(_uhoh) | 91:
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| 130 |
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.long SYM(_uhoh) | 92:
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| 131 |
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.long SYM(_uhoh) | 93:
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| 132 |
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.long SYM(_uhoh) | 94:
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| 133 |
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.long SYM(_uhoh) | 95:
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| 134 |
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.long SYM(_uhoh) | 96:
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| 135 |
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.long SYM(_uhoh) | 97:
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| 136 |
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.long SYM(_uhoh) | 98:
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| 137 |
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.long SYM(_uhoh) | 99:
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| 138 |
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.long SYM(_uhoh) | 100:
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| 139 |
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.long SYM(_uhoh) | 101:
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| 140 |
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.long SYM(_uhoh) | 102:
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| 141 |
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.long SYM(_uhoh) | 103:
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| 142 |
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.long SYM(_uhoh) | 104:
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| 143 |
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.long SYM(_uhoh) | 105:
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| 144 |
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.long SYM(_uhoh) | 106:
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| 145 |
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.long SYM(_uhoh) | 107:
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| 146 |
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.long SYM(_uhoh) | 108:
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| 147 |
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.long SYM(_uhoh) | 109:
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| 148 |
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.long SYM(_uhoh) | 110:
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| 149 |
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.long SYM(_uhoh) | 111:
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| 150 |
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.long SYM(_uhoh) | 112:
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| 151 |
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.long SYM(_uhoh) | 113:
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| 152 |
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.long SYM(_uhoh) | 114:
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| 153 |
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.long SYM(_uhoh) | 115:
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| 154 |
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.long SYM(_uhoh) | 116:
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| 155 |
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.long SYM(_uhoh) | 117:
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| 156 |
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.long SYM(_uhoh) | 118:
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| 157 |
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.long SYM(_uhoh) | 119:
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| 158 |
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.long SYM(_uhoh) | 120:
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| 159 |
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.long SYM(_uhoh) | 121:
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| 160 |
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.long SYM(_uhoh) | 122:
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| 161 |
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.long SYM(_uhoh) | 123:
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| 162 |
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.long SYM(_uhoh) | 124:
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| 163 |
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.long SYM(_uhoh) | 125:
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| 164 |
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.long SYM(_uhoh) | 126:
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| 165 |
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.long SYM(_uhoh) | 127:
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| 166 |
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.long SYM(_uhoh) | 128:
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| 167 |
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.long SYM(_uhoh) | 129:
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| 168 |
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.long SYM(_uhoh) | 130:
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| 169 |
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.long SYM(_uhoh) | 131:
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| 170 |
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.long SYM(_uhoh) | 132:
|
| 171 |
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.long SYM(_uhoh) | 133:
|
| 172 |
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.long SYM(_uhoh) | 134:
|
| 173 |
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.long SYM(_uhoh) | 135:
|
| 174 |
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.long SYM(_uhoh) | 136:
|
| 175 |
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.long SYM(_uhoh) | 137:
|
| 176 |
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.long SYM(_uhoh) | 138:
|
| 177 |
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.long SYM(_uhoh) | 139:
|
| 178 |
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.long SYM(_uhoh) | 140:
|
| 179 |
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.long SYM(_uhoh) | 141:
|
| 180 |
|
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.long SYM(_uhoh) | 142:
|
| 181 |
|
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.long SYM(_uhoh) | 143:
|
| 182 |
|
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.long SYM(_uhoh) | 144:
|
| 183 |
|
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.long SYM(_uhoh) | 145:
|
| 184 |
|
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.long SYM(_uhoh) | 146:
|
| 185 |
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.long SYM(_uhoh) | 147:
|
| 186 |
|
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.long SYM(_uhoh) | 148:
|
| 187 |
|
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.long SYM(_uhoh) | 149:
|
| 188 |
|
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.long SYM(_uhoh) | 150:
|
| 189 |
|
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.long SYM(_uhoh) | 151:
|
| 190 |
|
|
.long SYM(_uhoh) | 152:
|
| 191 |
|
|
.long SYM(_uhoh) | 153:
|
| 192 |
|
|
.long SYM(_uhoh) | 154:
|
| 193 |
|
|
.long SYM(_uhoh) | 155:
|
| 194 |
|
|
.long SYM(_uhoh) | 156:
|
| 195 |
|
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.long SYM(_uhoh) | 157:
|
| 196 |
|
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.long SYM(_uhoh) | 158:
|
| 197 |
|
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.long SYM(_uhoh) | 159:
|
| 198 |
|
|
.long SYM(_uhoh) | 160:
|
| 199 |
|
|
.long SYM(_uhoh) | 161:
|
| 200 |
|
|
.long SYM(_uhoh) | 162:
|
| 201 |
|
|
.long SYM(_uhoh) | 163:
|
| 202 |
|
|
.long SYM(_uhoh) | 164:
|
| 203 |
|
|
.long SYM(_uhoh) | 165:
|
| 204 |
|
|
.long SYM(_uhoh) | 166:
|
| 205 |
|
|
.long SYM(_uhoh) | 167:
|
| 206 |
|
|
.long SYM(_uhoh) | 168:
|
| 207 |
|
|
.long SYM(_uhoh) | 169:
|
| 208 |
|
|
.long SYM(_uhoh) | 170:
|
| 209 |
|
|
.long SYM(_uhoh) | 171:
|
| 210 |
|
|
.long SYM(_uhoh) | 172:
|
| 211 |
|
|
.long SYM(_uhoh) | 173:
|
| 212 |
|
|
.long SYM(_uhoh) | 174:
|
| 213 |
|
|
.long SYM(_uhoh) | 175:
|
| 214 |
|
|
.long SYM(_uhoh) | 176:
|
| 215 |
|
|
.long SYM(_uhoh) | 177:
|
| 216 |
|
|
.long SYM(_uhoh) | 178:
|
| 217 |
|
|
.long SYM(_uhoh) | 179:
|
| 218 |
|
|
.long SYM(_uhoh) | 180:
|
| 219 |
|
|
.long SYM(_uhoh) | 181:
|
| 220 |
|
|
.long SYM(_uhoh) | 182:
|
| 221 |
|
|
.long SYM(_uhoh) | 183:
|
| 222 |
|
|
.long SYM(_uhoh) | 184:
|
| 223 |
|
|
.long SYM(_uhoh) | 185:
|
| 224 |
|
|
.long SYM(_uhoh) | 186:
|
| 225 |
|
|
.long SYM(_uhoh) | 187:
|
| 226 |
|
|
.long SYM(_uhoh) | 188:
|
| 227 |
|
|
.long SYM(_uhoh) | 189:
|
| 228 |
|
|
.long SYM(_uhoh) | 190:
|
| 229 |
|
|
.long SYM(_uhoh) | 191:
|
| 230 |
|
|
.long SYM(_uhoh) | 192:
|
| 231 |
|
|
.long SYM(_uhoh) | 193:
|
| 232 |
|
|
.long SYM(_uhoh) | 194:
|
| 233 |
|
|
.long SYM(_uhoh) | 195:
|
| 234 |
|
|
.long SYM(_uhoh) | 196:
|
| 235 |
|
|
.long SYM(_uhoh) | 197:
|
| 236 |
|
|
.long SYM(_uhoh) | 198:
|
| 237 |
|
|
.long SYM(_uhoh) | 199:
|
| 238 |
|
|
.long SYM(_uhoh) | 200:
|
| 239 |
|
|
.long SYM(_uhoh) | 201:
|
| 240 |
|
|
.long SYM(_uhoh) | 202:
|
| 241 |
|
|
.long SYM(_uhoh) | 203:
|
| 242 |
|
|
.long SYM(_uhoh) | 204:
|
| 243 |
|
|
.long SYM(_uhoh) | 205:
|
| 244 |
|
|
.long SYM(_uhoh) | 206:
|
| 245 |
|
|
.long SYM(_uhoh) | 207:
|
| 246 |
|
|
.long SYM(_uhoh) | 208:
|
| 247 |
|
|
.long SYM(_uhoh) | 209:
|
| 248 |
|
|
.long SYM(_uhoh) | 210:
|
| 249 |
|
|
.long SYM(_uhoh) | 211:
|
| 250 |
|
|
.long SYM(_uhoh) | 212:
|
| 251 |
|
|
.long SYM(_uhoh) | 213:
|
| 252 |
|
|
.long SYM(_uhoh) | 214:
|
| 253 |
|
|
.long SYM(_uhoh) | 215:
|
| 254 |
|
|
.long SYM(_uhoh) | 216:
|
| 255 |
|
|
.long SYM(_uhoh) | 217:
|
| 256 |
|
|
.long SYM(_uhoh) | 218:
|
| 257 |
|
|
.long SYM(_uhoh) | 219:
|
| 258 |
|
|
.long SYM(_uhoh) | 220:
|
| 259 |
|
|
.long SYM(_uhoh) | 221:
|
| 260 |
|
|
.long SYM(_uhoh) | 222:
|
| 261 |
|
|
.long SYM(_uhoh) | 223:
|
| 262 |
|
|
.long SYM(_uhoh) | 224:
|
| 263 |
|
|
.long SYM(_uhoh) | 225:
|
| 264 |
|
|
.long SYM(_uhoh) | 226:
|
| 265 |
|
|
.long SYM(_uhoh) | 227:
|
| 266 |
|
|
.long SYM(_uhoh) | 228:
|
| 267 |
|
|
.long SYM(_uhoh) | 229:
|
| 268 |
|
|
.long SYM(_uhoh) | 230:
|
| 269 |
|
|
.long SYM(_uhoh) | 231:
|
| 270 |
|
|
.long SYM(_uhoh) | 232:
|
| 271 |
|
|
.long SYM(_uhoh) | 233:
|
| 272 |
|
|
.long SYM(_uhoh) | 234:
|
| 273 |
|
|
.long SYM(_uhoh) | 235:
|
| 274 |
|
|
.long SYM(_uhoh) | 236:
|
| 275 |
|
|
.long SYM(_uhoh) | 237:
|
| 276 |
|
|
.long SYM(_uhoh) | 238:
|
| 277 |
|
|
.long SYM(_uhoh) | 239:
|
| 278 |
|
|
.long SYM(_uhoh) | 240:
|
| 279 |
|
|
.long SYM(_uhoh) | 241:
|
| 280 |
|
|
.long SYM(_uhoh) | 242:
|
| 281 |
|
|
.long SYM(_uhoh) | 243:
|
| 282 |
|
|
.long SYM(_uhoh) | 244:
|
| 283 |
|
|
.long SYM(_uhoh) | 245:
|
| 284 |
|
|
.long SYM(_uhoh) | 246:
|
| 285 |
|
|
.long SYM(_uhoh) | 247:
|
| 286 |
|
|
.long SYM(_uhoh) | 248:
|
| 287 |
|
|
.long SYM(_uhoh) | 249:
|
| 288 |
|
|
.long SYM(_uhoh) | 250:
|
| 289 |
|
|
.long SYM(_uhoh) | 251:
|
| 290 |
|
|
.long SYM(_uhoh) | 252:
|
| 291 |
|
|
.long SYM(_uhoh) | 253:
|
| 292 |
|
|
.long SYM(_uhoh) | 254:
|
| 293 |
|
|
.long SYM(_uhoh) | 255:
|
| 294 |
|
|
|
| 295 |
|
|
/*
|
| 296 |
|
|
* Default trap handler
|
| 297 |
|
|
* With an oscilloscope you can see AS* stop
|
| 298 |
|
|
*/
|
| 299 |
|
|
PUBLIC (_uhoh)
|
| 300 |
|
|
SYM(_uhoh): nop | Leave spot for breakpoint
|
| 301 |
|
|
/* stop #0x2700 | Stop with interrupts disabled */
|
| 302 |
|
|
move.w #0x2700,sr
|
| 303 |
|
|
move.w (a7),_boot_panic_registers+4 | SR
|
| 304 |
|
|
move.l 2(a7),_boot_panic_registers | PC
|
| 305 |
|
|
move.w 6(a7),_boot_panic_registers+6 | format & vector
|
| 306 |
|
|
movem.l d0-d7/a0-a7, _boot_panic_registers+8
|
| 307 |
|
|
movec sfc, d0
|
| 308 |
|
|
movem.l d0, _boot_panic_registers+72
|
| 309 |
|
|
movec dfc, d0
|
| 310 |
|
|
movem.l d0, _boot_panic_registers+76
|
| 311 |
|
|
movec vbr, d0
|
| 312 |
|
|
movem.l d0, _boot_panic_registers+80
|
| 313 |
|
|
jmp SYM(_dbug_dumpanic)
|
| 314 |
|
|
bra.s _crt0_cold_start
|
| 315 |
|
|
|
| 316 |
|
|
/*
|
| 317 |
|
|
* Log, but otherwise ignore, spurious interrupts
|
| 318 |
|
|
*/
|
| 319 |
|
|
PUBLIC (_spuriousInterrupt)
|
| 320 |
|
|
SYM(_spuriousInterrupt):
|
| 321 |
|
|
addql #1,SYM(_M68kSpuriousInterruptCount)
|
| 322 |
|
|
rte
|
| 323 |
|
|
|
| 324 |
|
|
/*
|
| 325 |
|
|
* Place the low-order 3 octets of the board's ethernet address at
|
| 326 |
|
|
* a `well-known' fixed location relative to the startup location.
|
| 327 |
|
|
*/
|
| 328 |
|
|
.align 2
|
| 329 |
|
|
.word 0 | Padding
|
| 330 |
|
|
ethernet_address_buffer:
|
| 331 |
|
|
.word 0x08F3 | Default address
|
| 332 |
|
|
.word 0xDEAD
|
| 333 |
|
|
.word 0xCAFE
|
| 334 |
|
|
|
| 335 |
|
|
BEGIN_DATA
|
| 336 |
|
|
|
| 337 |
|
|
/* equates */
|
| 338 |
|
|
|
| 339 |
|
|
.equ _CPU340, 0x0
|
| 340 |
|
|
.equ _CPU349, 0x31
|
| 341 |
|
|
|
| 342 |
|
|
#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
|
| 343 |
|
|
.equ _EPLD_CS_BASE, 0x1
|
| 344 |
|
|
.equ _PROM_Start, 0x01000000 /* CS0 */
|
| 345 |
|
|
.equ _FLEX_Start, 0x08000000 /* CS2 */
|
| 346 |
|
|
.equ _I2C_Start, 0x0c000000 /* CS3 */
|
| 347 |
|
|
|
| 348 |
|
|
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
|
| 349 |
|
|
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
|
| 350 |
|
|
|
| 351 |
|
|
.equ _ExtRam_Start, 0x10000000 /* SRAM */
|
| 352 |
|
|
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
|
| 353 |
|
|
|
| 354 |
|
|
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
|
| 355 |
|
|
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
|
| 356 |
|
|
|
| 357 |
|
|
#else /* new addresses for AST68349 and 68340 */
|
| 358 |
|
|
|
| 359 |
|
|
.equ _EPLD_CS_BASE, 0x5
|
| 360 |
|
|
.equ _PROM_Start, 0x50000000 /* CS0 */
|
| 361 |
|
|
.equ _FLEX_Start, 0x08000000 /* CS2 */
|
| 362 |
|
|
.equ _I2C_Start, 0x0c000000 /* CS3 */
|
| 363 |
|
|
|
| 364 |
|
|
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
|
| 365 |
|
|
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
|
| 366 |
|
|
|
| 367 |
|
|
.equ _ExtRam_Start, 0x80000000 /* DRAM */
|
| 368 |
|
|
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
|
| 369 |
|
|
|
| 370 |
|
|
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
|
| 371 |
|
|
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
|
| 372 |
|
|
#endif
|
| 373 |
|
|
|
| 374 |
|
|
.equ _SPEED349, 0xD680 /* 24 Mhz */
|
| 375 |
|
|
.equ _SPEED340, 0xD700 /* 25 Mhz */
|
| 376 |
|
|
/* .equ _SPEED340, 0xCE00 16 Mhz */
|
| 377 |
|
|
|
| 378 |
|
|
#define crt0_boot_type d0 /* cold/warm start (must be D0) */
|
| 379 |
|
|
#define crt0_temp d1
|
| 380 |
|
|
#define crt0_cpu_type d2
|
| 381 |
|
|
#define crt0_csswitch d3
|
| 382 |
|
|
#define crt0_buswidth d4
|
| 383 |
|
|
#define crt0_pdcs d5
|
| 384 |
|
|
#define crt0_spare6 d6
|
| 385 |
|
|
#define crt0_spare7 d7
|
| 386 |
|
|
#define crt0_sim_base a0
|
| 387 |
|
|
#define crt0_glue a1
|
| 388 |
|
|
#define crt0_dram a2
|
| 389 |
|
|
#define crt0_ptr3 a3
|
| 390 |
|
|
#define crt0_ptr4 a4
|
| 391 |
|
|
#define crt0_ptr5 a5
|
| 392 |
|
|
#define crt0_ptr6 a6
|
| 393 |
|
|
|
| 394 |
|
|
/* -- PDCS buffer equates -- */
|
| 395 |
|
|
.equ pdcs_mask, 0x1F /* DRAM configuration */
|
| 396 |
|
|
.equ pdcs_sw12, 7 /* switch 12 */
|
| 397 |
|
|
.equ pdcs_sw11, 6 /* switch 11 */
|
| 398 |
|
|
.equ pdcs_sw14, 5 /* switch 14 */
|
| 399 |
|
|
|
| 400 |
|
|
.equ bit_cache, pdcs_sw12 /* enable cache if on */
|
| 401 |
|
|
.equ bit_meminit, pdcs_sw11 /* init memory if on */
|
| 402 |
|
|
|
| 403 |
|
|
/* -- Initialization stack and vars -- */
|
| 404 |
|
|
|
| 405 |
|
|
_AsteccBusWidth: ds.b 1
|
| 406 |
|
|
_AsteccCsSwitch: ds.b 1
|
| 407 |
|
|
_AsteccCpuName: ds.l 1
|
| 408 |
|
|
|
| 409 |
|
|
.align 4
|
| 410 |
|
|
|
| 411 |
|
|
_crt0_init_stack:
|
| 412 |
|
|
ds.l 500
|
| 413 |
|
|
_crt0_init_stktop:
|
| 414 |
|
|
|
| 415 |
|
|
/* -- Initialization code -- */
|
| 416 |
|
|
BEGIN_CODE
|
| 417 |
|
|
|
| 418 |
|
|
.align 4
|
| 419 |
|
|
dc.l _crt0_init_stktop /* reset SP */
|
| 420 |
|
|
dc.l _crt0_cold_start /* reset PC */
|
| 421 |
|
|
dc.l _crt0_warm_start
|
| 422 |
|
|
|
| 423 |
|
|
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards"
|
| 424 |
|
|
dc.w 0
|
| 425 |
|
|
.align 4
|
| 426 |
|
|
|
| 427 |
|
|
.globl start
|
| 428 |
|
|
start:
|
| 429 |
|
|
|
| 430 |
|
|
_crt0_cold_start:
|
| 431 |
|
|
moveq.l #0,crt0_boot_type | signal cold reset
|
| 432 |
|
|
bra.s _crt0_common_start
|
| 433 |
|
|
|
| 434 |
|
|
_crt0_warm_start:
|
| 435 |
|
|
moveq.l #1,crt0_boot_type | signal warm reset
|
| 436 |
|
|
|
| 437 |
|
|
_crt0_common_start:
|
| 438 |
|
|
move.w #0x2700,sr | disable interrupts and switch to interrupt mode
|
| 439 |
|
|
movea.l #_crt0_init_stktop,sp | set up initialization stack
|
| 440 |
|
|
|
| 441 |
|
|
move.l #Entry,crt0_temp | VBR initialization
|
| 442 |
|
|
movec.l crt0_temp,vbr |
|
| 443 |
|
|
moveq.l #0x07,crt0_temp
|
| 444 |
|
|
movec.l crt0_temp,dfc | prepare access in CPU space
|
| 445 |
|
|
move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES
|
| 446 |
|
|
moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795)
|
| 447 |
|
|
|
| 448 |
|
|
movea.l #BASE_SIM,crt0_sim_base
|
| 449 |
|
|
|
| 450 |
|
|
/* -- disable Bus Monitor -- */
|
| 451 |
|
|
move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register
|
| 452 |
|
|
|
| 453 |
|
|
/* -- enable A31-A24 -- */
|
| 454 |
|
|
clr.b SIM_PPRA1(crt0_sim_base)
|
| 455 |
|
|
|
| 456 |
|
|
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
|
| 457 |
|
|
move.w #0x427F,SIM_MCR(crt0_sim_base)
|
| 458 |
|
|
|
| 459 |
|
|
/* -- enable /IRQ3, 5, 6, 7 -- */
|
| 460 |
|
|
move.b #0xE8,SIM_PPRB(crt0_sim_base)
|
| 461 |
|
|
|
| 462 |
|
|
/* -- enable autovector on /IRQ7 -- */
|
| 463 |
|
|
move.b #0x80,SIM_AVR(crt0_sim_base)
|
| 464 |
|
|
|
| 465 |
|
|
/* -- test CPU type -- */
|
| 466 |
|
|
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
|
| 467 |
|
|
bne cpu_is_68340
|
| 468 |
|
|
|
| 469 |
|
|
/*-------------------------------------------------------------------------------------------*/
|
| 470 |
|
|
cpu_is_68349:
|
| 471 |
|
|
|
| 472 |
|
|
/* -- set cpu clock -- */
|
| 473 |
|
|
move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock
|
| 474 |
|
|
|
| 475 |
|
|
sync_wait349:
|
| 476 |
|
|
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
|
| 477 |
|
|
beq sync_wait349
|
| 478 |
|
|
|
| 479 |
|
|
/* to allow access to the EPLD internal registers, it is necessary
|
| 480 |
|
|
to disable the global chip-select /CS0 (which decodes every external
|
| 481 |
|
|
cycles). To do that, we initialize the 68349 internal RAM,
|
| 482 |
|
|
copy a part of the initialization code in it, and jump there.
|
| 483 |
|
|
from that moment, /CS0 is not used, therefore it can be initialized
|
| 484 |
|
|
with its default value. Its width may be incorrect, but it will be
|
| 485 |
|
|
adjusted later. The goal is to avoid any conflict with
|
| 486 |
|
|
the accesses to the EPLD registers.
|
| 487 |
|
|
When this is done, we read the RESET parameters (boot prom width
|
| 488 |
|
|
and chip-select switch) and proceed with the initialization
|
| 489 |
|
|
when all is done, we jump back to the boot prom now
|
| 490 |
|
|
decoded with a properly configured /CS0 */
|
| 491 |
|
|
|
| 492 |
|
|
/*-------------------------------------*/
|
| 493 |
|
|
/* -- configure internal SRAM banks -- */
|
| 494 |
|
|
|
| 495 |
|
|
move.l #0x00000000,QDMM_MCR(crt0_sim_base)
|
| 496 |
|
|
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
|
| 497 |
|
|
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
|
| 498 |
|
|
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
|
| 499 |
|
|
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
|
| 500 |
|
|
|
| 501 |
|
|
/*--------------------------------------------------------*/
|
| 502 |
|
|
/* -- copy to address of the 68349 initialization code -- */
|
| 503 |
|
|
|
| 504 |
|
|
lea.l _copy_start_code(%pc),crt0_ptr3
|
| 505 |
|
|
lea.l _copy_end_code(%pc),crt0_ptr4
|
| 506 |
|
|
move.l crt0_ptr4,crt0_temp
|
| 507 |
|
|
sub.l crt0_ptr3,crt0_temp
|
| 508 |
|
|
add.l #3,crt0_temp | adjust to next long word
|
| 509 |
|
|
lsr.l #2,crt0_temp
|
| 510 |
|
|
|
| 511 |
|
|
move.l #_FastRam_Start,crt0_ptr4
|
| 512 |
|
|
_copy_loop:
|
| 513 |
|
|
move.l (crt0_ptr3)+,(crt0_ptr4)+
|
| 514 |
|
|
subq.l #1,crt0_temp
|
| 515 |
|
|
bne.s _copy_loop
|
| 516 |
|
|
bra.l _FastRam_Start | jump to code in internal RAM
|
| 517 |
|
|
|
| 518 |
|
|
/*------------------------------------*/
|
| 519 |
|
|
/* -- start of initialization code -- */
|
| 520 |
|
|
|
| 521 |
|
|
_copy_start_code:
|
| 522 |
|
|
bra.l _begin_68349_init
|
| 523 |
|
|
|
| 524 |
|
|
/*----------------------------------------------------------*/
|
| 525 |
|
|
/* Astecc 68349 board : chip-select initialization values */
|
| 526 |
|
|
|
| 527 |
|
|
_table_csepld:
|
| 528 |
|
|
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
|
| 529 |
|
|
dc.b 0x80 | 16 bits, 0 ws
|
| 530 |
|
|
dc.b 0x90 | 16 bits, ext /dsack
|
| 531 |
|
|
dc.b 0x90 | 16 bits, ext /dsack
|
| 532 |
|
|
|
| 533 |
|
|
_table_cs349:
|
| 534 |
|
|
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
|
| 535 |
|
|
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
|
| 536 |
|
|
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
|
| 537 |
|
|
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
|
| 538 |
|
|
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
|
| 539 |
|
|
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
|
| 540 |
|
|
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
|
| 541 |
|
|
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
|
| 542 |
|
|
|
| 543 |
|
|
/*-------------------------------------------------*/
|
| 544 |
|
|
_begin_68349_init:
|
| 545 |
|
|
|
| 546 |
|
|
/*-------------------------------------------------*/
|
| 547 |
|
|
/* 68349 chip select initialization
|
| 548 |
|
|
|
| 549 |
|
|
at this stage, the width of /CS0 may be incorrect
|
| 550 |
|
|
it will be corrected later
|
| 551 |
|
|
*/
|
| 552 |
|
|
|
| 553 |
|
|
_cs68349_init:
|
| 554 |
|
|
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
|
| 555 |
|
|
lea.l _table_cs349(%pc),crt0_ptr3
|
| 556 |
|
|
|
| 557 |
|
|
moveq.l #0x07,crt0_temp
|
| 558 |
|
|
_cs349_init2:
|
| 559 |
|
|
move.l (crt0_ptr3)+,(crt0_ptr4)+
|
| 560 |
|
|
dbra crt0_temp,_cs349_init2
|
| 561 |
|
|
|
| 562 |
|
|
/*-----------------------------------------------*/
|
| 563 |
|
|
/* -- prepare access to the internal registers --*/
|
| 564 |
|
|
moveq.l #EPLD_SPACE,crt0_temp
|
| 565 |
|
|
movec.l crt0_temp,dfc
|
| 566 |
|
|
movec.l crt0_temp,sfc
|
| 567 |
|
|
move.l #GLUE_EPLD,crt0_glue
|
| 568 |
|
|
move.l #DRAM_EPLD,crt0_dram
|
| 569 |
|
|
|
| 570 |
|
|
/*-------------------------------------------*/
|
| 571 |
|
|
/* EPLD generated /CS[3..0] must be disabled */
|
| 572 |
|
|
|
| 573 |
|
|
_csepld_clear:
|
| 574 |
|
|
move.l crt0_glue,crt0_ptr4
|
| 575 |
|
|
move.w #3,crt0_spare6
|
| 576 |
|
|
clr.b crt0_temp
|
| 577 |
|
|
|
| 578 |
|
|
_csepld_clear1:
|
| 579 |
|
|
moves.b crt0_temp,(crt0_ptr4)+
|
| 580 |
|
|
dbra crt0_spare6,_csepld_clear1
|
| 581 |
|
|
|
| 582 |
|
|
/*---------------------------------------------------------*/
|
| 583 |
|
|
/* -- get width of boot PROM, and active chip-select set --*/
|
| 584 |
|
|
moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
|
| 585 |
|
|
move.b crt0_csswitch,crt0_buswidth
|
| 586 |
|
|
|
| 587 |
|
|
/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
|
| 588 |
|
|
: sel == 1 => EPLD chip_selects (/CS[3..0]) */
|
| 589 |
|
|
and.b #1,crt0_csswitch
|
| 590 |
|
|
|
| 591 |
|
|
/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
|
| 592 |
|
|
bus width : 32 16 8 ext./dsackx */
|
| 593 |
|
|
rol.b #2,crt0_buswidth
|
| 594 |
|
|
and.b #3,crt0_buswidth
|
| 595 |
|
|
|
| 596 |
|
|
/*----------------------------------------------------*/
|
| 597 |
|
|
/* -- configure chip select 0 with boot prom width -- */
|
| 598 |
|
|
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
|
| 599 |
|
|
lea.l _table_cs349(%pc),crt0_ptr3
|
| 600 |
|
|
move.l (crt0_ptr3)+,crt0_temp
|
| 601 |
|
|
and.b #0xFC,crt0_temp | clear PS0 & PS1
|
| 602 |
|
|
or.b crt0_buswidth,crt0_temp | set boot PROM bus width
|
| 603 |
|
|
move.l crt0_temp,(crt0_ptr4)+
|
| 604 |
|
|
|
| 605 |
|
|
/*------------------------*/
|
| 606 |
|
|
/* -- read PDCS buffer -- */
|
| 607 |
|
|
moves.b REG_PDCS(crt0_glue),crt0_pdcs
|
| 608 |
|
|
/* move.b #0x3F,crt0_pdcs pour test */
|
| 609 |
|
|
|
| 610 |
|
|
|
| 611 |
|
|
/*---------------------------------------*/
|
| 612 |
|
|
/* -- EPLD chip-select initialization -- */
|
| 613 |
|
|
/*---------------------------------------*/
|
| 614 |
|
|
btst.b #0,crt0_csswitch
|
| 615 |
|
|
beq _cs_init_end
|
| 616 |
|
|
|
| 617 |
|
|
/*--------------------------------------------*/
|
| 618 |
|
|
/* 68349 generated /CS[3..0] must be disabled */
|
| 619 |
|
|
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
|
| 620 |
|
|
lea.l _table_cs349(%pc),crt0_ptr3
|
| 621 |
|
|
moveq.l #0x03,crt0_temp
|
| 622 |
|
|
_cs349_clear:
|
| 623 |
|
|
move.l (crt0_ptr3)+,(crt0_ptr4)+
|
| 624 |
|
|
move.l (crt0_ptr3)+,crt0_spare6
|
| 625 |
|
|
and.b #0xFE,crt0_spare6 | disable chip-select
|
| 626 |
|
|
move.l crt0_spare6,(crt0_ptr4)+
|
| 627 |
|
|
dbra crt0_temp,_cs349_clear
|
| 628 |
|
|
|
| 629 |
|
|
/*---------------------------------------------*/
|
| 630 |
|
|
/* EPLD generated /CS[3..0] must be configured */
|
| 631 |
|
|
_csepld_init:
|
| 632 |
|
|
move.l crt0_glue,crt0_ptr4
|
| 633 |
|
|
lea.l _table_csepld(%pc),crt0_ptr3
|
| 634 |
|
|
|
| 635 |
|
|
move.b (crt0_ptr3)+,crt0_temp
|
| 636 |
|
|
or.b #0x20,crt0_temp | default width is 32 bits
|
| 637 |
|
|
tst.b crt0_buswidth | is boot PROM bus width 32 bits ?
|
| 638 |
|
|
beq _csepld1 | if not
|
| 639 |
|
|
and.b #0xDF,crt0_temp | set width to 16 bits
|
| 640 |
|
|
_csepld1:
|
| 641 |
|
|
moves.b crt0_temp,(crt0_ptr4)+
|
| 642 |
|
|
|
| 643 |
|
|
moveq.l #0x02,crt0_spare6
|
| 644 |
|
|
_csepld2:
|
| 645 |
|
|
move.b (crt0_ptr3)+,crt0_temp
|
| 646 |
|
|
moves.b crt0_temp,(crt0_ptr4)+
|
| 647 |
|
|
dbra crt0_spare6,_csepld2
|
| 648 |
|
|
|
| 649 |
|
|
_cs_init_end:
|
| 650 |
|
|
|
| 651 |
|
|
/*--------------------------------------*/
|
| 652 |
|
|
/* -- DRAM controller initialization -- */
|
| 653 |
|
|
_dram_init:
|
| 654 |
|
|
move.w #15,crt0_temp
|
| 655 |
|
|
move.l #_ExtRam_Start,crt0_ptr3
|
| 656 |
|
|
|
| 657 |
|
|
_dram_init1:
|
| 658 |
|
|
clr.l (crt0_ptr3)+ | must access DRAM
|
| 659 |
|
|
dbra crt0_temp,_dram_init1 | prior to init refresh
|
| 660 |
|
|
|
| 661 |
|
|
_dram_init2:
|
| 662 |
|
|
move.b #3,crt0_temp
|
| 663 |
|
|
moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states
|
| 664 |
|
|
|
| 665 |
|
|
move.b #0x81,crt0_temp
|
| 666 |
|
|
moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs
|
| 667 |
|
|
|
| 668 |
|
|
move.b #0,crt0_temp
|
| 669 |
|
|
moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes
|
| 670 |
|
|
|
| 671 |
|
|
/*-----------------------*/
|
| 672 |
|
|
/* -- configure cache -- */
|
| 673 |
|
|
_init_cache:
|
| 674 |
|
|
move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
|
| 675 |
|
|
btst.b #bit_cache,crt0_pdcs
|
| 676 |
|
|
bne _init_cache_end
|
| 677 |
|
|
or.l #0x00000001,CACHE_MCR(crt0_sim_base)
|
| 678 |
|
|
|
| 679 |
|
|
_init_cache_end:
|
| 680 |
|
|
|
| 681 |
|
|
/*-----------------------------*/
|
| 682 |
|
|
/* -- timers initialization -- */
|
| 683 |
|
|
|
| 684 |
|
|
clr.b crt0_temp
|
| 685 |
|
|
moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1
|
| 686 |
|
|
moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2
|
| 687 |
|
|
|
| 688 |
|
|
/*--------------------------*/
|
| 689 |
|
|
/* -- I2C initialization -- */
|
| 690 |
|
|
move.b #3,crt0_temp
|
| 691 |
|
|
moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports
|
| 692 |
|
|
|
| 693 |
|
|
/*-----------------------------------------*/
|
| 694 |
|
|
/* -- baudrate generator initialization -- */
|
| 695 |
|
|
move.b #2,crt0_temp
|
| 696 |
|
|
moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400
|
| 697 |
|
|
|
| 698 |
|
|
/*-------------------------------*/
|
| 699 |
|
|
/* -- IO port initialization -- */
|
| 700 |
|
|
clr.b crt0_temp
|
| 701 |
|
|
moves.b crt0_temp,REG_IO(crt0_glue) | set port as input
|
| 702 |
|
|
|
| 703 |
|
|
/* -- */
|
| 704 |
|
|
|
| 705 |
|
|
move.l #68349,crt0_cpu_type
|
| 706 |
|
|
|
| 707 |
|
|
|
| 708 |
|
|
/* -- jump back to PROM -- */
|
| 709 |
|
|
|
| 710 |
|
|
jmp.l (_fill_test) | must be absolute long
|
| 711 |
|
|
|
| 712 |
|
|
_copy_end_code:
|
| 713 |
|
|
|
| 714 |
|
|
/*-------------------------------------------------
|
| 715 |
|
|
initialization code for the 68340 board
|
| 716 |
|
|
-------------------------------------------------*/
|
| 717 |
|
|
|
| 718 |
|
|
/* Astecc 68340 board : chip-select initialization values */
|
| 719 |
|
|
_table_cs340:
|
| 720 |
|
|
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
|
| 721 |
|
|
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
|
| 722 |
|
|
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
|
| 723 |
|
|
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
|
| 724 |
|
|
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
|
| 725 |
|
|
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
|
| 726 |
|
|
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
|
| 727 |
|
|
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
|
| 728 |
|
|
|
| 729 |
|
|
cpu_is_68340:
|
| 730 |
|
|
|
| 731 |
|
|
/* -- set cpu clock -- */
|
| 732 |
|
|
move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock
|
| 733 |
|
|
sync_wait340:
|
| 734 |
|
|
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
|
| 735 |
|
|
beq sync_wait340
|
| 736 |
|
|
|
| 737 |
|
|
/* -- chip select initialization -- */
|
| 738 |
|
|
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
|
| 739 |
|
|
lea.l _table_cs340(%pc),crt0_ptr3
|
| 740 |
|
|
moveq.l #0x07,crt0_temp
|
| 741 |
|
|
_b_cs340:
|
| 742 |
|
|
move.l (crt0_ptr3)+,crt0_ptr5
|
| 743 |
|
|
move.l crt0_ptr5,(crt0_ptr4)+ | pour test
|
| 744 |
|
|
dbra crt0_temp,_b_cs340
|
| 745 |
|
|
|
| 746 |
|
|
move.l #68340,crt0_cpu_type
|
| 747 |
|
|
move.b #0,crt0_csswitch | CPU
|
| 748 |
|
|
move.b #1,crt0_buswidth | 16 bits
|
| 749 |
|
|
|
| 750 |
|
|
|
| 751 |
|
|
/*-------------------------------------------------
|
| 752 |
|
|
fill RAM if COLDSTART
|
| 753 |
|
|
-------------------------------------------------*/
|
| 754 |
|
|
_fill_test:
|
| 755 |
|
|
|
| 756 |
|
|
tst.l crt0_boot_type
|
| 757 |
|
|
bne _dont_fill
|
| 758 |
|
|
|
| 759 |
|
|
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
|
| 760 |
|
|
bne _fill
|
| 761 |
|
|
btst.b #bit_meminit,crt0_pdcs
|
| 762 |
|
|
bne _dont_fill
|
| 763 |
|
|
|
| 764 |
|
|
/* fill main memory */
|
| 765 |
|
|
_fill:
|
| 766 |
|
|
move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars
|
| 767 |
|
|
move.l #_ExtRam_Start,crt0_temp
|
| 768 |
|
|
sub.l #_crt0_init_stack,crt0_temp
|
| 769 |
|
|
add.l #_ExtRam_Size,crt0_temp | get size
|
| 770 |
|
|
lsr.l #2,crt0_temp | ajust for long word
|
| 771 |
|
|
_fill_loop:
|
| 772 |
|
|
clr.l (crt0_ptr3)+
|
| 773 |
|
|
subq.l #1,crt0_temp
|
| 774 |
|
|
bne _fill_loop
|
| 775 |
|
|
|
| 776 |
|
|
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
|
| 777 |
|
|
bne _fill_bccram
|
| 778 |
|
|
|
| 779 |
|
|
/* fill QDMM memory */
|
| 780 |
|
|
movea.l #_FastRam_Start,crt0_ptr3 | get start
|
| 781 |
|
|
move.l #_FastRam_Size,crt0_temp | get size
|
| 782 |
|
|
lsr.l #2,crt0_temp | ajust for long word
|
| 783 |
|
|
|
| 784 |
|
|
_QDMMfill_loop:
|
| 785 |
|
|
clr.l (crt0_ptr3)+
|
| 786 |
|
|
subq.l #1,crt0_temp
|
| 787 |
|
|
bne _QDMMfill_loop
|
| 788 |
|
|
bra _dont_fill
|
| 789 |
|
|
|
| 790 |
|
|
/* fill BCC memory */
|
| 791 |
|
|
_fill_bccram:
|
| 792 |
|
|
movea.l #_BCCram_Start,crt0_ptr3 | get start
|
| 793 |
|
|
move.l #_BCCram_Size,crt0_temp | get size
|
| 794 |
|
|
lsr.l #2,crt0_temp | ajust for long word
|
| 795 |
|
|
_BCCfill_loop:
|
| 796 |
|
|
clr.l (crt0_ptr3)+
|
| 797 |
|
|
subq.l #1,crt0_temp
|
| 798 |
|
|
bne _BCCfill_loop
|
| 799 |
|
|
|
| 800 |
|
|
*-------------------------------------------------*/
|
| 801 |
|
|
_dont_fill:
|
| 802 |
|
|
move.b crt0_csswitch,_AsteccCsSwitch
|
| 803 |
|
|
move.b crt0_buswidth,_AsteccBusWidth
|
| 804 |
|
|
move.l crt0_cpu_type,_AsteccCpuName
|
| 805 |
|
|
|
| 806 |
|
|
jmp SYM(_Init68340) | Start C code (which never returns)
|
| 807 |
|
|
|
| 808 |
|
|
/*
|
| 809 |
|
|
* Copy DATA segment, clear BSS segment, set up real stack,
|
| 810 |
|
|
* initialize heap, start C program.
|
| 811 |
|
|
* Assume that DATA and BSS sizes are multiples of 4.
|
| 812 |
|
|
*/
|
| 813 |
|
|
PUBLIC (_CopyDataClearBSSAndStart)
|
| 814 |
|
|
SYM(_CopyDataClearBSSAndStart):
|
| 815 |
|
|
lea SYM(_copy_start),a0 | Get start of DATA in RAM
|
| 816 |
|
|
lea SYM(_etext),a2 | Get start of DATA in ROM
|
| 817 |
|
|
cmpl a0,a2 | Are they the same?
|
| 818 |
|
|
beq.s NOCOPY | Yes, no copy necessary
|
| 819 |
|
|
lea SYM(_copy_end),a1 | Get end of DATA in RAM
|
| 820 |
|
|
bra.s COPYLOOPTEST | Branch into copy loop
|
| 821 |
|
|
COPYLOOP:
|
| 822 |
|
|
movel a2@+,a0@+ | Copy word from ROM to RAM
|
| 823 |
|
|
COPYLOOPTEST:
|
| 824 |
|
|
cmpl a1,a0 | Done?
|
| 825 |
|
|
bcs.s COPYLOOP | No, skip
|
| 826 |
|
|
NOCOPY:
|
| 827 |
|
|
|
| 828 |
|
|
lea _clear_start,a0 | Get start of BSS
|
| 829 |
|
|
lea _clear_end,a1 | Get end of BSS
|
| 830 |
|
|
clrl d0 | Value to set
|
| 831 |
|
|
bra.s ZEROLOOPTEST | Branch into clear loop
|
| 832 |
|
|
ZEROLOOP:
|
| 833 |
|
|
movel d0,a0@+ | Clear a word
|
| 834 |
|
|
ZEROLOOPTEST:
|
| 835 |
|
|
cmpl a1,a0 | Done?
|
| 836 |
|
|
bcs.s ZEROLOOP | No, skip
|
| 837 |
|
|
|
| 838 |
|
|
movel #_stack_init,a7 | set master stack pointer
|
| 839 |
|
|
movel d0,a7@- | environp
|
| 840 |
|
|
movel d0,a7@- | argv
|
| 841 |
|
|
movel d0,a7@- | argc
|
| 842 |
|
|
jsr SYM(boot_card) | Call C main
|
| 843 |
|
|
|
| 844 |
|
|
PUBLIC (_mainDone)
|
| 845 |
|
|
SYM(_mainDone):
|
| 846 |
|
|
nop | Leave spot for breakpoint
|
| 847 |
|
|
movew #1,a7 | Force a double bus error
|
| 848 |
|
|
movel d0,a7@- | This should cause a RESET
|
| 849 |
|
|
/* stop #0x2700 | Stop with interrupts disabled */
|
| 850 |
|
|
move.w #0x2700,sr
|
| 851 |
|
|
bra.l SYM(_mainDone) | Stuck forever
|
| 852 |
|
|
|
| 853 |
|
|
.align 2
|
| 854 |
|
|
BEGIN_DATA_DCL
|
| 855 |
|
|
.align 2
|
| 856 |
|
|
PUBLIC (environ)
|
| 857 |
|
|
SYM (environ):
|
| 858 |
|
|
.long 0
|
| 859 |
|
|
PUBLIC (_M68kSpuriousInterruptCount)
|
| 860 |
|
|
SYM (_M68kSpuriousInterruptCount):
|
| 861 |
|
|
.long 0
|
| 862 |
|
|
END_DATA_DCL
|
| 863 |
|
|
|
| 864 |
|
|
END
|
| 865 |
|
|
|
