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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [gen68340/] [start/] [startfor340only.S] - Blame information for rev 173

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Line No. Rev Author Line
1 30 unneback
/*
2
 *  This file contains the entry point for the application.
3
 *  The name of this entry point is compiler dependent.
4
 *  It jumps to the BSP which is responsible for performing
5
 *  all initialization.
6
 *
7
 *  COPYRIGHT (c) 1989-1999.
8
 *  On-Line Applications Research Corporation (OAR).
9
 *
10
 *  The license and distribution terms for this file may in
11
 *  the file LICENSE in this distribution or at
12
 *  http://www.OARcorp.com/rtems/license.html.
13
 *
14
 * Based on the `gen68360' board support package, and covered by the
15
 * original distribution terms.
16
 *
17
 * Geoffroy Montel
18
 * France Telecom - CNET/DSM/TAM/CAT
19
 * 4, rue du Clos Courtel
20
 * 35512 CESSON-SEVIGNE
21
 * FRANCE
22
 *
23
 * e-mail: g_montel@yahoo.com
24
 *
25
 *  $Id: startfor340only.S,v 1.2 2001-09-27 12:00:07 chris Exp $
26
 */
27
 
28
#include "asm.h"
29
#include 
30
 
31
BEGIN_CODE
32
        /*
33
         * Step 1: Decide on Reset Stack Pointer and Initial Program Counter
34
         */
35
Entry:
36
        .long   SYM(m340)+1024          |   0: Initial SSP
37
        .long   start                   |   1: Initial PC
38
        .long   SYM(_uhoh)              |   2: Bus error
39
        .long   SYM(_uhoh)              |   3: Address error
40
        .long   SYM(_uhoh)              |   4: Illegal instruction
41
        .long   SYM(_uhoh)              |   5: Zero division
42
        .long   SYM(_uhoh)              |   6: CHK, CHK2 instruction
43
        .long   SYM(_uhoh)              |   7: TRAPcc, TRAPV instructions
44
        .long   SYM(_uhoh)              |   8: Privilege violation
45
        .long   SYM(_uhoh)              |   9: Trace
46
        .long   SYM(_uhoh)              |  10: Line 1010 emulator
47
        .long   SYM(_uhoh)              |  11: Line 1111 emulator
48
        .long   SYM(_uhoh)              |  12: Hardware breakpoint
49
        .long   SYM(_uhoh)              |  13: Reserved for coprocessor violation
50
        .long   SYM(_uhoh)              |  14: Format error
51
        .long   SYM(_uhoh)              |  15: Uninitialized interrupt
52
        .long   SYM(_uhoh)              |  16: Unassigned, reserved
53
        .long   SYM(_uhoh)              |  17:
54
        .long   SYM(_uhoh)              |  18:
55
        .long   SYM(_uhoh)              |  19:
56
        .long   SYM(_uhoh)              |  20:
57
        .long   SYM(_uhoh)              |  21:
58
        .long   SYM(_uhoh)              |  22:
59
        .long   SYM(_uhoh)              |  23:
60
        .long   SYM(_spuriousInterrupt) |  24: Spurious interrupt
61
        .long   SYM(_uhoh)              |  25: Level 1 interrupt autovector
62
        .long   SYM(_uhoh)              |  26: Level 2 interrupt autovector
63
        .long   SYM(_uhoh)              |  27: Level 3 interrupt autovector
64
        .long   SYM(_uhoh)              |  28: Level 4 interrupt autovector
65
        .long   SYM(_uhoh)              |  29: Level 5 interrupt autovector
66
        .long   SYM(_uhoh)              |  30: Level 6 interrupt autovector
67
        .long   SYM(_uhoh)              |  31: Level 7 interrupt autovector
68
        .long   SYM(_uhoh)              |  32: Trap instruction (0-15)
69
        .long   SYM(_uhoh)              |  33:
70
        .long   SYM(_uhoh)              |  34:
71
        .long   SYM(_uhoh)              |  35:
72
        .long   SYM(_uhoh)              |  36:
73
        .long   SYM(_uhoh)              |  37:
74
        .long   SYM(_uhoh)              |  38:
75
        .long   SYM(_uhoh)              |  39:
76
        .long   SYM(_uhoh)              |  40:
77
        .long   SYM(_uhoh)              |  41:
78
        .long   SYM(_uhoh)              |  42:
79
        .long   SYM(_uhoh)              |  43:
80
        .long   SYM(_uhoh)              |  44:
81
        .long   SYM(_uhoh)              |  45:
82
        .long   SYM(_uhoh)              |  46:
83
        .long   SYM(_uhoh)              |  47:
84
        .long   SYM(_uhoh)              |  48: Reserved for coprocessor
85
        .long   SYM(_uhoh)              |  49:
86
        .long   SYM(_uhoh)              |  50:
87
        .long   SYM(_uhoh)              |  51:
88
        .long   SYM(_uhoh)              |  52:
89
        .long   SYM(_uhoh)              |  53:
90
        .long   SYM(_uhoh)              |  54:
91
        .long   SYM(_uhoh)              |  55:
92
        .long   SYM(_uhoh)              |  56:
93
        .long   SYM(_uhoh)              |  57:
94
        .long   SYM(_uhoh)              |  58:
95
        .long   SYM(_uhoh)              |  59: Unassigned, reserved
96
        .long   SYM(_uhoh)              |  60:
97
        .long   SYM(_uhoh)              |  61:
98
        .long   SYM(_uhoh)              |  62:
99
        .long   SYM(_uhoh)              |  63:
100
        .long   SYM(_uhoh)              |  64: User defined vectors (192)
101
        .long   SYM(_uhoh)              |  65:
102
        .long   SYM(_uhoh)              |  66:
103
        .long   SYM(_uhoh)              |  67:
104
        .long   SYM(_uhoh)              |  68:
105
        .long   SYM(_uhoh)              |  69:
106
        .long   SYM(_uhoh)              |  70:
107
        .long   SYM(_uhoh)              |  71:
108
        .long   SYM(_uhoh)              |  72:
109
        .long   SYM(_uhoh)              |  73:
110
        .long   SYM(_uhoh)              |  74:
111
        .long   SYM(_uhoh)              |  75:
112
        .long   SYM(_uhoh)              |  76:
113
        .long   SYM(_uhoh)              |  77:
114
        .long   SYM(_uhoh)              |  78:
115
        .long   SYM(_uhoh)              |  79:
116
        .long   SYM(_uhoh)              |  80:
117
        .long   SYM(_uhoh)              |  81:
118
        .long   SYM(_uhoh)              |  82:
119
        .long   SYM(_uhoh)              |  83:
120
        .long   SYM(_uhoh)              |  84:
121
        .long   SYM(_uhoh)              |  85:
122
        .long   SYM(_uhoh)              |  86:
123
        .long   SYM(_uhoh)              |  87:
124
        .long   SYM(_uhoh)              |  88:
125
        .long   SYM(_uhoh)              |  89:
126
        .long   SYM(_uhoh)              |  90:
127
        .long   SYM(_uhoh)              |  91:
128
        .long   SYM(_uhoh)              |  92:
129
        .long   SYM(_uhoh)              |  93:
130
        .long   SYM(_uhoh)              |  94:
131
        .long   SYM(_uhoh)              |  95:
132
        .long   SYM(_uhoh)              |  96:
133
        .long   SYM(_uhoh)              |  97:
134
        .long   SYM(_uhoh)              |  98:
135
        .long   SYM(_uhoh)              |  99:
136
        .long   SYM(_uhoh)              | 100:
137
        .long   SYM(_uhoh)              | 101:
138
        .long   SYM(_uhoh)              | 102:
139
        .long   SYM(_uhoh)              | 103:
140
        .long   SYM(_uhoh)              | 104:
141
        .long   SYM(_uhoh)              | 105:
142
        .long   SYM(_uhoh)              | 106:
143
        .long   SYM(_uhoh)              | 107:
144
        .long   SYM(_uhoh)              | 108:
145
        .long   SYM(_uhoh)              | 109:
146
        .long   SYM(_uhoh)              | 110:
147
        .long   SYM(_uhoh)              | 111:
148
        .long   SYM(_uhoh)              | 112:
149
        .long   SYM(_uhoh)              | 113:
150
        .long   SYM(_uhoh)              | 114:
151
        .long   SYM(_uhoh)              | 115:
152
        .long   SYM(_uhoh)              | 116:
153
        .long   SYM(_uhoh)              | 117:
154
        .long   SYM(_uhoh)              | 118:
155
        .long   SYM(_uhoh)              | 119:
156
        .long   SYM(_uhoh)              | 120:
157
        .long   SYM(_uhoh)              | 121:
158
        .long   SYM(_uhoh)              | 122:
159
        .long   SYM(_uhoh)              | 123:
160
        .long   SYM(_uhoh)              | 124:
161
        .long   SYM(_uhoh)              | 125:
162
        .long   SYM(_uhoh)              | 126:
163
        .long   SYM(_uhoh)              | 127:
164
        .long   SYM(_uhoh)              | 128:
165
        .long   SYM(_uhoh)              | 129:
166
        .long   SYM(_uhoh)              | 130:
167
        .long   SYM(_uhoh)              | 131:
168
        .long   SYM(_uhoh)              | 132:
169
        .long   SYM(_uhoh)              | 133:
170
        .long   SYM(_uhoh)              | 134:
171
        .long   SYM(_uhoh)              | 135:
172
        .long   SYM(_uhoh)              | 136:
173
        .long   SYM(_uhoh)              | 137:
174
        .long   SYM(_uhoh)              | 138:
175
        .long   SYM(_uhoh)              | 139:
176
        .long   SYM(_uhoh)              | 140:
177
        .long   SYM(_uhoh)              | 141:
178
        .long   SYM(_uhoh)              | 142:
179
        .long   SYM(_uhoh)              | 143:
180
        .long   SYM(_uhoh)              | 144:
181
        .long   SYM(_uhoh)              | 145:
182
        .long   SYM(_uhoh)              | 146:
183
        .long   SYM(_uhoh)              | 147:
184
        .long   SYM(_uhoh)              | 148:
185
        .long   SYM(_uhoh)              | 149:
186
        .long   SYM(_uhoh)              | 150:
187
        .long   SYM(_uhoh)              | 151:
188
        .long   SYM(_uhoh)              | 152:
189
        .long   SYM(_uhoh)              | 153:
190
        .long   SYM(_uhoh)              | 154:
191
        .long   SYM(_uhoh)              | 155:
192
        .long   SYM(_uhoh)              | 156:
193
        .long   SYM(_uhoh)              | 157:
194
        .long   SYM(_uhoh)              | 158:
195
        .long   SYM(_uhoh)              | 159:
196
        .long   SYM(_uhoh)              | 160:
197
        .long   SYM(_uhoh)              | 161:
198
        .long   SYM(_uhoh)              | 162:
199
        .long   SYM(_uhoh)              | 163:
200
        .long   SYM(_uhoh)              | 164:
201
        .long   SYM(_uhoh)              | 165:
202
        .long   SYM(_uhoh)              | 166:
203
        .long   SYM(_uhoh)              | 167:
204
        .long   SYM(_uhoh)              | 168:
205
        .long   SYM(_uhoh)              | 169:
206
        .long   SYM(_uhoh)              | 170:
207
        .long   SYM(_uhoh)              | 171:
208
        .long   SYM(_uhoh)              | 172:
209
        .long   SYM(_uhoh)              | 173:
210
        .long   SYM(_uhoh)              | 174:
211
        .long   SYM(_uhoh)              | 175:
212
        .long   SYM(_uhoh)              | 176:
213
        .long   SYM(_uhoh)              | 177:
214
        .long   SYM(_uhoh)              | 178:
215
        .long   SYM(_uhoh)              | 179:
216
        .long   SYM(_uhoh)              | 180:
217
        .long   SYM(_uhoh)              | 181:
218
        .long   SYM(_uhoh)              | 182:
219
        .long   SYM(_uhoh)              | 183:
220
        .long   SYM(_uhoh)              | 184:
221
        .long   SYM(_uhoh)              | 185:
222
        .long   SYM(_uhoh)              | 186:
223
        .long   SYM(_uhoh)              | 187:
224
        .long   SYM(_uhoh)              | 188:
225
        .long   SYM(_uhoh)              | 189:
226
        .long   SYM(_uhoh)              | 190:
227
        .long   SYM(_uhoh)              | 191:
228
        .long   SYM(_uhoh)              | 192:
229
        .long   SYM(_uhoh)              | 193:
230
        .long   SYM(_uhoh)              | 194:
231
        .long   SYM(_uhoh)              | 195:
232
        .long   SYM(_uhoh)              | 196:
233
        .long   SYM(_uhoh)              | 197:
234
        .long   SYM(_uhoh)              | 198:
235
        .long   SYM(_uhoh)              | 199:
236
        .long   SYM(_uhoh)              | 200:
237
        .long   SYM(_uhoh)              | 201:
238
        .long   SYM(_uhoh)              | 202:
239
        .long   SYM(_uhoh)              | 203:
240
        .long   SYM(_uhoh)              | 204:
241
        .long   SYM(_uhoh)              | 205:
242
        .long   SYM(_uhoh)              | 206:
243
        .long   SYM(_uhoh)              | 207:
244
        .long   SYM(_uhoh)              | 208:
245
        .long   SYM(_uhoh)              | 209:
246
        .long   SYM(_uhoh)              | 210:
247
        .long   SYM(_uhoh)              | 211:
248
        .long   SYM(_uhoh)              | 212:
249
        .long   SYM(_uhoh)              | 213:
250
        .long   SYM(_uhoh)              | 214:
251
        .long   SYM(_uhoh)              | 215:
252
        .long   SYM(_uhoh)              | 216:
253
        .long   SYM(_uhoh)              | 217:
254
        .long   SYM(_uhoh)              | 218:
255
        .long   SYM(_uhoh)              | 219:
256
        .long   SYM(_uhoh)              | 220:
257
        .long   SYM(_uhoh)              | 221:
258
        .long   SYM(_uhoh)              | 222:
259
        .long   SYM(_uhoh)              | 223:
260
        .long   SYM(_uhoh)              | 224:
261
        .long   SYM(_uhoh)              | 225:
262
        .long   SYM(_uhoh)              | 226:
263
        .long   SYM(_uhoh)              | 227:
264
        .long   SYM(_uhoh)              | 228:
265
        .long   SYM(_uhoh)              | 229:
266
        .long   SYM(_uhoh)              | 230:
267
        .long   SYM(_uhoh)              | 231:
268
        .long   SYM(_uhoh)              | 232:
269
        .long   SYM(_uhoh)              | 233:
270
        .long   SYM(_uhoh)              | 234:
271
        .long   SYM(_uhoh)              | 235:
272
        .long   SYM(_uhoh)              | 236:
273
        .long   SYM(_uhoh)              | 237:
274
        .long   SYM(_uhoh)              | 238:
275
        .long   SYM(_uhoh)              | 239:
276
        .long   SYM(_uhoh)              | 240:
277
        .long   SYM(_uhoh)              | 241:
278
        .long   SYM(_uhoh)              | 242:
279
        .long   SYM(_uhoh)              | 243:
280
        .long   SYM(_uhoh)              | 244:
281
        .long   SYM(_uhoh)              | 245:
282
        .long   SYM(_uhoh)              | 246:
283
        .long   SYM(_uhoh)              | 247:
284
        .long   SYM(_uhoh)              | 248:
285
        .long   SYM(_uhoh)              | 249:
286
        .long   SYM(_uhoh)              | 250:
287
        .long   SYM(_uhoh)              | 251:
288
        .long   SYM(_uhoh)              | 252:
289
        .long   SYM(_uhoh)              | 253:
290
        .long   SYM(_uhoh)              | 254:
291
        .long   SYM(_uhoh)              | 255:
292
 
293
/*
294
 * Default trap handler
295
 * With an oscilloscope you can see AS* stop
296
 */
297
        PUBLIC (_uhoh)
298
SYM(_uhoh):     nop                             | Leave spot for breakpoint
299
        stop    #0x2700                         | Stop with interrupts disabled
300
        bra.s   SYM(_uhoh)                      | Stuck forever
301
 
302
/*
303
 * Log, but otherwise ignore, spurious interrupts
304
 */
305
        PUBLIC (_spuriousInterrupt)
306
SYM(_spuriousInterrupt):
307
        addql   #1,SYM(_M68kSpuriousInterruptCount)
308
        rte
309
 
310
/*
311
 * Place the low-order 3 octets of the board's ethernet address at
312
 * a `well-known' fixed location relative to the startup location.
313
 */
314
        .align 2
315
        .word   0                        | Padding
316
ethernet_address_buffer:
317
        .word   0x08F3                  | Default address
318
        .word   0xDEAD
319
        .word   0xCAFE
320
 
321
/* -- equates -- */
322
.equ    _PROM_Start,    0x01000000       /* CS0 */
323
.equ    _BCCram_Start,  0x00000000       /* CS1 */
324
.equ    _FLEX_Start,    0x08000000       /* CS2 */
325
.equ    _I2C_Start,     0x02000000       /* CS3 */
326
.equ    _EXTram_Start,  0x10000000       /* CS4 */
327
.equ    _EXTram_Size,   0x000400000      /* 4 Mbytes */
328
.equ    _SPEED, 0xD780                   /* 25 Mhz CPU349 */
329
/* .equ _SPEED, 0xD700                      25 Mhz */
330
/* .equ _SPEED, 0xCE00                      16 Mhz */
331
 
332
BEGIN_DATA
333
 
334
_crt0_init_stack:
335
                ds.l    0x1000
336
_crt0_init_stktop:
337
 
338
 
339
BEGIN_CODE
340
        dc.l    _crt0_init_stktop        /* reset SP */
341
        dc.l    _crt0_cold_start         /* reset PC */
342
        dc.l    _crt0_warm_start
343
 
344
        .ascii  "RTEMS"
345
        dc.w    0
346
 
347
.align 2
348
 
349
_table_cs:
350
        /* carte Astecc - 68340 */
351
        dc.l    0x003FFFF0                              /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
352
/*      dc.l    0x003FFFFD                               Mask CS0 (4Mbytes PROM, 16bits, 3WS)   */
353
        dc.l    ((_PROM_Start&0xFFFFFF00)+0x00000003)   /* Base CS0 */
354
/*      dc.l    0x0000FFF1                               MASK CS1 (RAMBCC340, 0WS, FTE) */
355
        dc.l    0x0000FFFD                              /* MASK CS1 (RAMBCC340, 0WS, FTE) */
356
/*      dc.l    ((_BCCram_Start&0xFFFFFF00)+0x00000007)  Base CS1 */
357
        dc.l    ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
358
        dc.l    0x000000FF                              /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
359
        dc.l    ((_FLEX_Start&0xFFFFFF00)+0x00000003)   /* Base CS2 */
360
        dc.l    0x000000FF                              /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
361
        dc.l    ((_I2C_Start&0xFFFFFF00)+0x00000003)    /* Base CS3 */
362
 
363
/*
364
 * Initial PC
365
 */
366
.globl start
367
start:
368
 
369
_crt0_cold_start:
370
        moveq.l #0,d0                                   /* signal cold reset */
371
        bra.s   _crt0_common_start
372
 
373
_crt0_warm_start:
374
        moveq.l #1,d0                                   /* signal warm reset */
375
 
376
_crt0_common_start:
377
        move.w  #0x2700,sr                              /* disable interrupts and switch to interrupt mode */
378
        movea.l #_crt0_init_stktop,sp                   /* set up initialization stack */
379
 
380
        lea     Entry,a0                                /* Get base of vector table */
381
        movec   a0,vbr                                  /* Set up the VBR */
382
 
383
        moveq.l #0x07,d1
384
        movec.l d1,dfc                                  /* prepare access in CPU space */
385
        move.l  #(BASE_SIM+1),d1
386
        moves.l d1,BASE_REG                             /* base initialization (must be MOVES, PCC-130795) */
387
        moveq.l #0x05,d1
388
        movec.l d1,dfc
389
 
390
        movea.l #BASE_SIM,a0
391
 
392
        /* -- disable Bus Monitor -- */
393
        move.b  #0,SIM_SYPCR(a0)                        /* system protection control register */
394
 
395
        /* -- set frequency to 25.16 Mhz -- */
396
        move.w  #_SPEED,SIM_SYNCR(a0)                   /* clock */
397
 
398
sync_wait:
399
        btst.b  #3,(SIM_SYNCR+1)(a0)
400
        beq     sync_wait
401
 
402
        /* -- enable A31-A24 -- */
403
        clr.b   SIM_PPRA1(a0)
404
 
405
        /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
406
        move.w  #0x427F,SIM_MCR(a0)
407
 
408
        /* -- chip select initialization -- */
409
        lea.l   SIM_MASKH0(a0),a2
410
        lea.l   _table_cs(%pc),a1
411
 
412
        moveq.l #0x07,d1
413
 
414
_b_cs:
415
        move.l  (a1)+, (a2)+
416
        dbra    d1,_b_cs
417
 
418
        /* fill RAM if COLDSTART */
419
        tst.l   d0
420
        bne     _dont_fill
421
 
422
        movea.l #_EXTram_Start,a0                       /* get start */
423
        move.l  #_EXTram_Size,d1                        /* get size */
424
        lsr.l   #2,d1                                   /* ajust for long word */
425
 
426
_fill_loop:
427
        clr.l   (a0)+
428
        subq.l  #1,d1
429
        bne     _fill_loop
430
 
431
_dont_fill:
432
        jmp     SYM(_Init68340)         | Start C code (which never returns)
433
 
434
/*
435
 * Copy DATA segment, clear BSS segment, set up real stack,
436
 * initialize heap, start C program.
437
 * Assume that DATA and BSS sizes are multiples of 4.
438
 */
439
        PUBLIC (_CopyDataClearBSSAndStart)
440
SYM(_CopyDataClearBSSAndStart):
441
        lea     copy_start,a0           | Get start of DATA in RAM
442
        lea     SYM(etext),a2           | Get start of DATA in ROM
443
        cmpl    a0,a2                   | Are they the same?
444
        beq.s   NOCOPY                  | Yes, no copy necessary
445
        lea     copy_end,a1             | Get end of DATA in RAM
446
        bra.s   COPYLOOPTEST            | Branch into copy loop
447
COPYLOOP:
448
        movel   a2@+,a0@+               | Copy word from ROM to RAM
449
COPYLOOPTEST:
450
        cmpl    a1,a0                   | Done?
451
        bcs.s   COPYLOOP                | No, skip
452
NOCOPY:
453
 
454
        lea     clear_start,a0          | Get start of BSS
455
        lea     clear_end,a1            | Get end of BSS
456
        clrl    d0                      | Value to set
457
        bra.s   ZEROLOOPTEST            | Branch into clear loop
458
ZEROLOOP:
459
        movel   d0,a0@+                 | Clear a word
460
ZEROLOOPTEST:
461
        cmpl    a1,a0                   | Done?
462
        bcs.s   ZEROLOOP                | No, skip
463
 
464
        movel   #stack_init,a7          | set master stack pointer
465
        movel   d0,a7@-                 | environp
466
        movel   d0,a7@-                 | argv
467
        movel   d0,a7@-                 | argc
468
        jsr     SYM(boot_card)          | Call C main
469
 
470
        PUBLIC (_mainDone)
471
SYM(_mainDone):
472
        nop                             | Leave spot for breakpoint
473
        movew   #1,a7                   | Force a double bus error
474
        movel   d0,a7@-                 | This should cause a RESET
475
        stop    #0x2700                 | Stop with interrupts disabled
476
        bra.s   SYM(_mainDone)          | Stuck forever
477
 
478
        .align 2
479
 
480
BEGIN_DATA_DCL
481
        .align 2
482
        PUBLIC (environ)
483
SYM (environ):
484
        .long   0
485
        PUBLIC (_M68kSpuriousInterruptCount)
486
SYM (_M68kSpuriousInterruptCount):
487
        .long   0
488
END_DATA_DCL
489
 
490
END
491
 

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