| 1 |
30 |
unneback |
/*
|
| 2 |
|
|
* Timer_init()
|
| 3 |
|
|
*
|
| 4 |
|
|
* ATTENTION: AS MC68349 has no built-in Timer, the following code doesn't work
|
| 5 |
|
|
* in a MC68349. You can't use FIFO full mode for the moment, but
|
| 6 |
|
|
* it should be easy to fix this by using an external timer
|
| 7 |
|
|
*
|
| 8 |
|
|
* Use TIMER 1 for TIMEOUT when using FIFO FULL mode in UART driver
|
| 9 |
|
|
* Use TIMER 2 for timing test suites
|
| 10 |
|
|
*
|
| 11 |
|
|
* Geoffroy Montel
|
| 12 |
|
|
* France Telecom - CNET/DSM/TAM/CAT
|
| 13 |
|
|
* 4, rue du Clos Courtel
|
| 14 |
|
|
* 35512 CESSON-SEVIGNE
|
| 15 |
|
|
* FRANCE
|
| 16 |
|
|
*
|
| 17 |
|
|
* e-mail: g_montel@yahoo.com
|
| 18 |
|
|
*
|
| 19 |
|
|
* $Id: timer.c,v 1.2 2001-09-27 12:00:07 chris Exp $
|
| 20 |
|
|
*/
|
| 21 |
|
|
|
| 22 |
|
|
/*
|
| 23 |
|
|
*
|
| 24 |
|
|
* Input parameters: NONE
|
| 25 |
|
|
*
|
| 26 |
|
|
* Output parameters: NONE
|
| 27 |
|
|
*
|
| 28 |
|
|
* NOTE: It is important that the timer start/stop overhead be
|
| 29 |
|
|
* determined when porting or modifying this code.
|
| 30 |
|
|
*
|
| 31 |
|
|
* COPYRIGHT (c) 1989-1999.
|
| 32 |
|
|
* On-Line Applications Research Corporation (OAR).
|
| 33 |
|
|
*
|
| 34 |
|
|
* The license and distribution terms for this file may be
|
| 35 |
|
|
* found in the file LICENSE in this distribution or at
|
| 36 |
|
|
* http://www.OARcorp.com/rtems/license.html.
|
| 37 |
|
|
*/
|
| 38 |
|
|
|
| 39 |
|
|
#include <rtems.h>
|
| 40 |
|
|
#include <bsp.h>
|
| 41 |
|
|
#include <m340uart.h>
|
| 42 |
|
|
#include <m340timer.h>
|
| 43 |
|
|
#include <m68340.h>
|
| 44 |
|
|
|
| 45 |
|
|
#define TIMER1_VECTOR 122
|
| 46 |
|
|
#define TIMER1_IRQ_LEVEL 5
|
| 47 |
|
|
#define TIMER1_INTERRUPT_ARBITRATION 5
|
| 48 |
|
|
|
| 49 |
|
|
#define TIMER2_VECTOR 123
|
| 50 |
|
|
#define TIMER2_IRQ_LEVEL 4
|
| 51 |
|
|
#define TIMER2_INTERRUPT_ARBITRATION 4
|
| 52 |
|
|
|
| 53 |
|
|
#define CLOCK_SPEED 25 /* in Mhz */
|
| 54 |
|
|
|
| 55 |
|
|
#define max(a,b) (((a)>(b)) ? (a) : (b))
|
| 56 |
|
|
|
| 57 |
|
|
void (*Restart_Fifo_Full_A_Timer)();
|
| 58 |
|
|
void (*Restart_Check_A_Timer)();
|
| 59 |
|
|
void (*Restart_Fifo_Full_B_Timer)();
|
| 60 |
|
|
void (*Restart_Check_B_Timer)();
|
| 61 |
|
|
|
| 62 |
|
|
int preload = 0;
|
| 63 |
|
|
|
| 64 |
|
|
/******************************************************
|
| 65 |
|
|
Name: __Restart_Fifo_Full_Timer
|
| 66 |
|
|
Input parameters: -
|
| 67 |
|
|
Output parameters: -
|
| 68 |
|
|
Description: when a character is received, sets
|
| 69 |
|
|
the TIMER to raise an interrupt at
|
| 70 |
|
|
TIMEOUT.
|
| 71 |
|
|
It's necessary to prevent from not
|
| 72 |
|
|
getting n-1 characters (with n the
|
| 73 |
|
|
Uart Fifo size)
|
| 74 |
|
|
*****************************************************/
|
| 75 |
|
|
void __Restart_Fifo_Full_Timer (void)
|
| 76 |
|
|
{
|
| 77 |
|
|
TSR1 |= m340_TO;
|
| 78 |
|
|
TCR1 &= ~m340_CPE;
|
| 79 |
|
|
WPREL11 = preload;
|
| 80 |
|
|
TCR1 |= m340_CPE;
|
| 81 |
|
|
}
|
| 82 |
|
|
|
| 83 |
|
|
/******************************************************
|
| 84 |
|
|
Name: __Restart_Fifo_Full_Timer
|
| 85 |
|
|
Input parameters: -
|
| 86 |
|
|
Output parameters: -
|
| 87 |
|
|
Description: when no character has been received
|
| 88 |
|
|
recently, check now and then if whether
|
| 89 |
|
|
a there's a character in the FIFO
|
| 90 |
|
|
*****************************************************/
|
| 91 |
|
|
void __Restart_Check_Timer (void)
|
| 92 |
|
|
{
|
| 93 |
|
|
TSR1 |= m340_TO;
|
| 94 |
|
|
TCR1 &= ~m340_CPE;
|
| 95 |
|
|
WPREL11 = 0xFFFF;
|
| 96 |
|
|
TCR1 |= m340_CPE;
|
| 97 |
|
|
}
|
| 98 |
|
|
|
| 99 |
|
|
/******************************************************
|
| 100 |
|
|
Name: __do_nothing
|
| 101 |
|
|
Input parameters: -
|
| 102 |
|
|
Output parameters: -
|
| 103 |
|
|
Description: we always restart the fifo full timer
|
| 104 |
|
|
with a call to Restart_*_Timer
|
| 105 |
|
|
if we do not use FIFO full, Restart_*_Timer
|
| 106 |
|
|
are set to do __do_nothing
|
| 107 |
|
|
*****************************************************/
|
| 108 |
|
|
void __do_nothing (void)
|
| 109 |
|
|
{
|
| 110 |
|
|
}
|
| 111 |
|
|
|
| 112 |
|
|
#define Fifo_Full_on_A (m340_uart_config[UART_CHANNEL_A].rx_mode==UART_FIFO_FULL && m340_uart_config[UART_CHANNEL_A].enable && m340_uart_config[UART_CHANNEL_A].mode==UART_INTERRUPTS)
|
| 113 |
|
|
#define Fifo_Full_on_B (m340_uart_config[UART_CHANNEL_B].rx_mode==UART_FIFO_FULL && m340_uart_config[UART_CHANNEL_B].enable && m340_uart_config[UART_CHANNEL_B].mode==UART_INTERRUPTS)
|
| 114 |
|
|
|
| 115 |
|
|
/******************************************************
|
| 116 |
|
|
Name: Fifo_Full_Timer_initialize
|
| 117 |
|
|
Input parameters: -
|
| 118 |
|
|
Output parameters: -
|
| 119 |
|
|
Description: initialize Timer 1 for FIFO full mode
|
| 120 |
|
|
*****************************************************/
|
| 121 |
|
|
void Fifo_Full_Timer_initialize (void)
|
| 122 |
|
|
{
|
| 123 |
|
|
float max_baud_rate;
|
| 124 |
|
|
int prescaler_output_tap = -1;
|
| 125 |
|
|
int nb_of_clock_ticks = 0;
|
| 126 |
|
|
|
| 127 |
|
|
/*
|
| 128 |
|
|
* USE TIMER 1 for UART FIFO FULL mode
|
| 129 |
|
|
*/
|
| 130 |
|
|
|
| 131 |
|
|
if ( Fifo_Full_on_A || Fifo_Full_on_B )
|
| 132 |
|
|
{
|
| 133 |
|
|
/* Disable the timer */
|
| 134 |
|
|
TCR1 &= ~m340_SWR;
|
| 135 |
|
|
|
| 136 |
|
|
/* Reset the interrupts */
|
| 137 |
|
|
TSR1 &= ~(m340_TO | m340_TG | m340_TC);
|
| 138 |
|
|
|
| 139 |
|
|
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
|
| 140 |
|
|
set interrupt arbitration */
|
| 141 |
|
|
TMCR1 = TIMER1_INTERRUPT_ARBITRATION;
|
| 142 |
|
|
|
| 143 |
|
|
/* interrupt priority level and interrupt vector */
|
| 144 |
|
|
TIR1 = TIMER1_VECTOR | (TIMER1_IRQ_LEVEL << 8);
|
| 145 |
|
|
|
| 146 |
|
|
/* compute prescaler */
|
| 147 |
|
|
if ( Fifo_Full_on_A && Fifo_Full_on_B)
|
| 148 |
|
|
max_baud_rate = max(m340_uart_config[UART_CHANNEL_A].rx_baudrate, m340_uart_config[UART_CHANNEL_B].rx_baudrate);
|
| 149 |
|
|
else if ( Fifo_Full_on_A )
|
| 150 |
|
|
max_baud_rate = m340_uart_config[UART_CHANNEL_A].rx_baudrate;
|
| 151 |
|
|
else max_baud_rate = m340_uart_config[UART_CHANNEL_B].rx_baudrate;
|
| 152 |
|
|
|
| 153 |
|
|
/* find out config */
|
| 154 |
|
|
nb_of_clock_ticks = (10/max_baud_rate)*(CLOCK_SPEED*1000000)*1.2;
|
| 155 |
|
|
if (nb_of_clock_ticks < 0xFFFF) {
|
| 156 |
|
|
preload = nb_of_clock_ticks;
|
| 157 |
|
|
prescaler_output_tap = -1;
|
| 158 |
|
|
} else if (nb_of_clock_ticks/2 < 0xFFFF) {
|
| 159 |
|
|
preload = nb_of_clock_ticks/2;
|
| 160 |
|
|
prescaler_output_tap = m340_Divide_by_2;
|
| 161 |
|
|
} else if (nb_of_clock_ticks/4 < 0xFFFF) {
|
| 162 |
|
|
preload = nb_of_clock_ticks/4;
|
| 163 |
|
|
prescaler_output_tap = m340_Divide_by_4;
|
| 164 |
|
|
} else if (nb_of_clock_ticks/8 < 0xFFFF) {
|
| 165 |
|
|
preload = nb_of_clock_ticks/8;
|
| 166 |
|
|
prescaler_output_tap = m340_Divide_by_16;
|
| 167 |
|
|
} else if (nb_of_clock_ticks/16 < 0xFFFF) {
|
| 168 |
|
|
preload = nb_of_clock_ticks/16;
|
| 169 |
|
|
prescaler_output_tap = m340_Divide_by_16;
|
| 170 |
|
|
} else if (nb_of_clock_ticks/32 < 0xFFFF) {
|
| 171 |
|
|
preload = nb_of_clock_ticks/32;
|
| 172 |
|
|
prescaler_output_tap = m340_Divide_by_32;
|
| 173 |
|
|
} else if (nb_of_clock_ticks/64 < 0xFFFF) {
|
| 174 |
|
|
preload = nb_of_clock_ticks/64;
|
| 175 |
|
|
prescaler_output_tap = m340_Divide_by_64;
|
| 176 |
|
|
} else if (nb_of_clock_ticks/128 < 0xFFFF) {
|
| 177 |
|
|
preload = nb_of_clock_ticks/128;
|
| 178 |
|
|
prescaler_output_tap = m340_Divide_by_128;
|
| 179 |
|
|
} else if (nb_of_clock_ticks/256 < 0xFFFF) {
|
| 180 |
|
|
preload = nb_of_clock_ticks/256;
|
| 181 |
|
|
prescaler_output_tap = m340_Divide_by_256;
|
| 182 |
|
|
}
|
| 183 |
|
|
|
| 184 |
|
|
/* Input Capture/Output Compare (ICOC) */
|
| 185 |
|
|
TCR1 = m340_SWR | m340_TO_Enabled | m340_ICOC;
|
| 186 |
|
|
if (prescaler_output_tap!=-1) TCR1 |= prescaler_output_tap | m340_PSE;
|
| 187 |
|
|
|
| 188 |
|
|
/* install interrupt vector */
|
| 189 |
|
|
{
|
| 190 |
|
|
rtems_isr_entry old_handler;
|
| 191 |
|
|
rtems_status_code sc;
|
| 192 |
|
|
|
| 193 |
|
|
extern void _Debug_ISR_Handler_Console(void);
|
| 194 |
|
|
|
| 195 |
|
|
sc = rtems_interrupt_catch (InterruptHandler,
|
| 196 |
|
|
TIMER1_VECTOR,
|
| 197 |
|
|
&old_handler);
|
| 198 |
|
|
|
| 199 |
|
|
/* uncomment this if you want to pass control to your own ISR handler
|
| 200 |
|
|
it may be usefull to do so to check for performances with an oscilloscope */
|
| 201 |
|
|
/*
|
| 202 |
|
|
{
|
| 203 |
|
|
proc_ptr ignored;
|
| 204 |
|
|
_CPU_ISR_install_raw_handler( TIMER1_VECTOR, _Debug_ISR_Handler_Console, &ignored );
|
| 205 |
|
|
}
|
| 206 |
|
|
*/
|
| 207 |
|
|
}
|
| 208 |
|
|
} /* fifo full mode on a uart */
|
| 209 |
|
|
|
| 210 |
|
|
/* install routines */
|
| 211 |
|
|
Restart_Check_A_Timer = Fifo_Full_on_A ? __Restart_Check_Timer : __do_nothing;
|
| 212 |
|
|
Restart_Fifo_Full_A_Timer = Fifo_Full_on_A ? __Restart_Fifo_Full_Timer : __do_nothing;
|
| 213 |
|
|
Restart_Check_B_Timer = Fifo_Full_on_B ? __Restart_Check_Timer : __do_nothing;
|
| 214 |
|
|
Restart_Fifo_Full_B_Timer = Fifo_Full_on_B ? __Restart_Fifo_Full_Timer : __do_nothing;
|
| 215 |
|
|
/* start checking timer */
|
| 216 |
|
|
Restart_Check_A_Timer();
|
| 217 |
|
|
Restart_Check_B_Timer();
|
| 218 |
|
|
}
|
| 219 |
|
|
|
| 220 |
|
|
/******************************************************
|
| 221 |
|
|
Name: Timer_initialize
|
| 222 |
|
|
Input parameters: -
|
| 223 |
|
|
Output parameters: -
|
| 224 |
|
|
Description: init Timer for timing test suites
|
| 225 |
|
|
*****************************************************/
|
| 226 |
|
|
void Timer_initialize (void)
|
| 227 |
|
|
{
|
| 228 |
|
|
/* Disable the timer */
|
| 229 |
|
|
TCR2 &= ~m340_SWR;
|
| 230 |
|
|
|
| 231 |
|
|
/* Reset the interrupts */
|
| 232 |
|
|
TSR2 &= ~(m340_TO | m340_TG | m340_TC);
|
| 233 |
|
|
|
| 234 |
|
|
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
|
| 235 |
|
|
set interrupt arbitration */
|
| 236 |
|
|
TMCR1 = TIMER2_INTERRUPT_ARBITRATION;
|
| 237 |
|
|
|
| 238 |
|
|
/* interrupt priority level and interrupt vector */
|
| 239 |
|
|
TIR1 = TIMER2_VECTOR | (TIMER2_IRQ_LEVEL << 8);
|
| 240 |
|
|
|
| 241 |
|
|
/* Init the stop bit for normal operation, ignore FREEZE, user privileges,
|
| 242 |
|
|
set interrupt arbitration */
|
| 243 |
|
|
TMCR2 = TIMER2_INTERRUPT_ARBITRATION;
|
| 244 |
|
|
|
| 245 |
|
|
/* Preload register 1 */
|
| 246 |
|
|
WPREL21 = 0xFFFF;
|
| 247 |
|
|
|
| 248 |
|
|
/* Input Capture/Output Compare (ICOC) */
|
| 249 |
|
|
TCR2 = m340_SWR | m340_ICOC | m340_PSE | m340_Divide_by_16 | m340_CPE;
|
| 250 |
|
|
}
|
| 251 |
|
|
|
| 252 |
|
|
/******************************************************
|
| 253 |
|
|
Name: Read_timer
|
| 254 |
|
|
Input parameters: -
|
| 255 |
|
|
Output parameters: -
|
| 256 |
|
|
Description: Return timer value in microsecond units
|
| 257 |
|
|
*****************************************************/
|
| 258 |
|
|
int
|
| 259 |
|
|
Read_timer (void)
|
| 260 |
|
|
{
|
| 261 |
|
|
/* there's CLOCK_SPEED / 16 micro seconds between two timer register decrement */
|
| 262 |
|
|
return (((0xFFFF - TCNTR2) * CLOCK_SPEED) / 16);
|
| 263 |
|
|
}
|
| 264 |
|
|
|
| 265 |
|
|
/******************************************************
|
| 266 |
|
|
Name: Empty_function
|
| 267 |
|
|
Input parameters: -
|
| 268 |
|
|
Output parameters: -
|
| 269 |
|
|
Description: Empty function call used in loops to
|
| 270 |
|
|
measure basic cost of looping
|
| 271 |
|
|
in Timing Test Suite.
|
| 272 |
|
|
*****************************************************/
|
| 273 |
|
|
rtems_status_code
|
| 274 |
|
|
Empty_function (void)
|
| 275 |
|
|
{
|
| 276 |
|
|
return RTEMS_SUCCESSFUL;
|
| 277 |
|
|
}
|
| 278 |
|
|
|
| 279 |
|
|
/******************************************************
|
| 280 |
|
|
Name: Set_find_average_overhead
|
| 281 |
|
|
Input parameters: -
|
| 282 |
|
|
Output parameters: -
|
| 283 |
|
|
Description: -
|
| 284 |
|
|
*****************************************************/
|
| 285 |
|
|
void
|
| 286 |
|
|
Set_find_average_overhead(rtems_boolean find_flag)
|
| 287 |
|
|
{
|
| 288 |
|
|
}
|