OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [idp/] [timer/] [timerisr.S] - Blame information for rev 562

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  timer_isr()
2
 *
3
 *  This routine provides the ISR for the MC68230 timer on the Motorola
4
 *  IDP board.   The timer is set up to generate an interrupt at maximum
5
 *  intervals.
6
 *
7
 *  Code modified by Doug McBride, Colorado Space Grant College
8
 *  countdown should be loaded automatically
9
 *
10
 *  Input parameters:  NONE
11
 *
12
 *  Output parameters:  NONE
13
 *
14
 *  COPYRIGHT (c) 1989-1999.
15
 *  On-Line Applications Research Corporation (OAR).
16
 *
17
 *  The license and distribution terms for this file may be
18
 *  found in the file LICENSE in this distribution or at
19
 *  http://www.OARcorp.com/rtems/license.html.
20
 *
21
 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:12 chris Exp $
22
 */
23
 
24
#include "asm.h"
25
 
26
BEGIN_CODE
27
 
28
.set TSR,        0x00c0106B              | base address of PIT register "TSR"
29
 
30
        PUBLIC (timerisr)
31
SYM (timerisr):
32
        movb    #1,TSR                                         | acknowledge interrupt
33
        addql   #1, SYM (Ttimer_val)   | increment timer value
34
        rte
35
 
36
END_CODE
37
END

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.