OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147/] [startup/] [bspclean.c] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  This routine returns control to 147Bug.
3
 *
4
 *  COPYRIGHT (c) 1989-1999.
5
 *  On-Line Applications Research Corporation (OAR).
6
 *
7
 *  The license and distribution terms for this file may be
8
 *  found in the file LICENSE in this distribution or at
9
 *  http://www.OARcorp.com/rtems/license.html.
10
 *
11
 *  MVME147 port for TNI - Telecom Bretagne
12
 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
13
 *  May 1996
14
 *
15
 *  $Id: bspclean.c,v 1.2 2001-09-27 12:00:16 chris Exp $
16
 */
17
 
18
#include <rtems.h>
19
#include <bsp.h>
20
#include <clockdrv.h>
21
 
22
void bsp_return_to_monitor_trap()
23
{
24
  extern void start( void  );
25
 
26
  register volatile void *start_addr;
27
 
28
  m68k_set_vbr( 0 );                /* restore 147Bug vectors */
29
  asm volatile( "trap   #15"  );    /* trap to 147Bug */
30
  asm volatile( ".short 0x63" );    /* return to 147Bug (.RETURN) */
31
                                    /* restart program */
32
  start_addr = start;
33
 
34
  asm volatile ( "jmp %0@" : "=a" (start_addr) : "0" (start_addr) );
35
}
36
 
37
void bsp_cleanup( void )
38
{
39
   pcc->timer1_int_control = 0; /* Disable Timer 1 */
40
   pcc->timer2_int_control = 0; /* Disable Timer 2 */
41
 
42
   M68Kvec[ 45 ] = bsp_return_to_monitor_trap;   /* install handler */
43
   asm volatile( "trap #13" );  /* insures SUPV mode */
44
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.