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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147/] [timer/] [timerisr.S] - Blame information for rev 173

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/*  timer_isr()
 *
 *  This routine provides the ISR for the PCC timer on the MVME147
 *  board.   The timer is set up to generate an interrupt at maximum
 *  intervals.
 *
 *  MVME147 port for TNI - Telecom Bretagne
 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
 *  May 1996
 *
 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:16 chris Exp $
 */
 
#include "asm.h"
 
BEGIN_CODE
 
.set T1_CONTROL_REGISTER,  0xfffe1018    | timer 1 control register
 
        PUBLIC (timerisr)
SYM (timerisr):
        orb     #0x80, T1_CONTROL_REGISTER | clear T1 int status bit
        addql   #1, SYM (Ttimer_val)     | increment timer value
end_timerisr:
        rte
 
END_CODE
END

Line No.	Rev	Author	Line
1	30	unneback	`/* timer_isr()`
2			`*`
3			`* This routine provides the ISR for the PCC timer on the MVME147`
4			`* board. The timer is set up to generate an interrupt at maximum`
5			`* intervals.`
6			`*`
7			`* MVME147 port for TNI - Telecom Bretagne`
8			`* by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)`
9			`* May 1996`
10			`*`
11			`* $Id: timerisr.S,v 1.2 2001-09-27 12:00:16 chris Exp $`
12			`*/`
13
14			`#include "asm.h"`
15
16			`BEGIN_CODE`
17
18			`.set T1_CONTROL_REGISTER, 0xfffe1018 \| timer 1 control register`
19
20			`PUBLIC (timerisr)`
21			`SYM (timerisr):`
22			`orb #0x80, T1_CONTROL_REGISTER \| clear T1 int status bit`
23			`addql #1, SYM (Ttimer_val) \| increment timer value`
24			`end_timerisr:`
25			`rte`
26
27			`END_CODE`
28			`END`

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147/] [timer/] [timerisr.S] - Blame information for rev 173