OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147/] [timer/] [timerisr.S] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  timer_isr()
2
 *
3
 *  This routine provides the ISR for the PCC timer on the MVME147
4
 *  board.   The timer is set up to generate an interrupt at maximum
5
 *  intervals.
6
 *
7
 *  MVME147 port for TNI - Telecom Bretagne
8
 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
9
 *  May 1996
10
 *
11
 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:16 chris Exp $
12
 */
13
 
14
#include "asm.h"
15
 
16
BEGIN_CODE
17
 
18
.set T1_CONTROL_REGISTER,  0xfffe1018    | timer 1 control register
19
 
20
        PUBLIC (timerisr)
21
SYM (timerisr):
22
        orb     #0x80, T1_CONTROL_REGISTER | clear T1 int status bit
23
        addql   #1, SYM (Ttimer_val)     | increment timer value
24
end_timerisr:
25
        rte
26
 
27
END_CODE
28
END

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.