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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147/] [timer/] [timerisr.S] - Blame information for rev 30

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/*  timer_isr()
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 *
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 *  This routine provides the ISR for the PCC timer on the MVME147
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 *  board.   The timer is set up to generate an interrupt at maximum
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 *  intervals.
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 *
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 *  MVME147 port for TNI - Telecom Bretagne
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 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
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 *  May 1996
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 *
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 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:16 chris Exp $
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 */
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#include "asm.h"
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BEGIN_CODE
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.set T1_CONTROL_REGISTER,  0xfffe1018    | timer 1 control register
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        PUBLIC (timerisr)
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SYM (timerisr):
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        orb     #0x80, T1_CONTROL_REGISTER | clear T1 int status bit
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        addql   #1, SYM (Ttimer_val)     | increment timer value
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end_timerisr:
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        rte
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END_CODE
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END

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