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/*  bsp.h
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 *
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 *  This include file contains all MVME147 board IO definitions.
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 *
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 *  COPYRIGHT (c) 1989-1999.
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 *  On-Line Applications Research Corporation (OAR).
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  MVME147 port for TNI - Telecom Bretagne
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 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
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 *  May 1996
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 *
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 *  $Id: bsp.h,v 1.2 2001-09-27 12:00:17 chris Exp $
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 */
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#ifndef __MVME147_h
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#define __MVME147_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtems.h>
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#include <clockdrv.h>
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#include <console.h>
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#include <iosupp.h>
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/*
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 *  confdefs.h overrides for this BSP:
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 *   - number of termios serial ports (defaults to 1)
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 *   - Interrupt stack space is not minimum if defined.
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 */
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/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
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#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
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/* Constants */
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#define RAM_START 0x00007000
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#define RAM_END   0x003e0000
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#define DRAM_END  0x00400000
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  /* We leave 128k for the shared memory */
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  /* MVME 147 Peripheral controller chip
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     see MVME147/D1, 3.4 */
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struct pcc_map {
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  /* 32 bit registers */
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  rtems_unsigned32 dma_table_address;            /* 0xfffe1000 */
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  rtems_unsigned32 dma_data_address;             /* 0xfffe1004 */
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  rtems_unsigned32 dma_bytecount;                /* 0xfffe1008 */
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  rtems_unsigned32 dma_data_holding;             /* 0xfffe100c */
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  /* 16 bit registers */
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  rtems_unsigned16 timer1_preload;               /* 0xfffe1010 */
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  rtems_unsigned16 timer1_count;                 /* 0xfffe1012 */
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  rtems_unsigned16 timer2_preload;               /* 0xfffe1014 */
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  rtems_unsigned16 timer2_count;                 /* 0xfffe1016 */
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  /* 8 bit registers */
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  rtems_unsigned8 timer1_int_control;            /* 0xfffe1018 */
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  rtems_unsigned8 timer1_control;                /* 0xfffe1019 */
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  rtems_unsigned8 timer2_int_control;            /* 0xfffe101a */
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  rtems_unsigned8 timer2_control;                /* 0xfffe101b */
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  rtems_unsigned8 acfail_int_control;            /* 0xfffe101c */
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  rtems_unsigned8 watchdog_control;              /* 0xfffe101d */
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  rtems_unsigned8 printer_int_control;           /* 0xfffe101e */
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  rtems_unsigned8 printer_control;               /* 0xfffe102f */
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  rtems_unsigned8 dma_int_control;               /* 0xfffe1020 */
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  rtems_unsigned8 dma_control;                   /* 0xfffe1021 */
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  rtems_unsigned8 bus_error_int_control;         /* 0xfffe1022 */
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  rtems_unsigned8 dma_status;                    /* 0xfffe1023 */
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  rtems_unsigned8 abort_int_control;             /* 0xfffe1024 */
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  rtems_unsigned8 table_address_function_code;   /* 0xfffe1025 */
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  rtems_unsigned8 serial_port_int_control;       /* 0xfffe1026 */
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  rtems_unsigned8 general_purpose_control;       /* 0xfffe1027 */
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  rtems_unsigned8 lan_int_control;               /* 0xfffe1028 */
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  rtems_unsigned8 general_purpose_status;        /* 0xfffe1029 */
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  rtems_unsigned8 scsi_port_int_control;         /* 0xfffe102a */
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  rtems_unsigned8 slave_base_address;            /* 0xfffe102b */
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  rtems_unsigned8 software_int_1_control;        /* 0xfffe102c */
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  rtems_unsigned8 int_base_vector;               /* 0xfffe102d */
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  rtems_unsigned8 software_int_2_control;        /* 0xfffe102e */
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  rtems_unsigned8 revision_level;                /* 0xfffe102f */
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};
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#define pcc      ((volatile struct pcc_map * const) 0xfffe1000)
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/* VME chip configuration registers */
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struct vme_lcsr_map {
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  rtems_unsigned8 unused_1;
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  rtems_unsigned8 system_controller;             /* 0xfffe2001 */
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  rtems_unsigned8 unused_2;
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  rtems_unsigned8 vme_bus_requester;             /* 0xfffe2003 */
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  rtems_unsigned8 unused_3;
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  rtems_unsigned8 master_configuration;          /* 0xfffe2005 */
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  rtems_unsigned8 unused_4;
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  rtems_unsigned8 slave_configuration;           /* 0xfffe2007 */
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  rtems_unsigned8 unused_5;
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  rtems_unsigned8 timer_configuration;           /* 0xfffe2009 */
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  rtems_unsigned8 unused_6;
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  rtems_unsigned8 slave_address_modifier;        /* 0xfffe200b */
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  rtems_unsigned8 unused_7;
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  rtems_unsigned8 master_address_modifier;       /* 0xfffe200d */
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  rtems_unsigned8 unused_8;
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  rtems_unsigned8 interrupt_handler_mask;        /* 0xfffe200f */
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  rtems_unsigned8 unused_9;
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  rtems_unsigned8 utility_interrupt_mask;        /* 0xfffe2011 */
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  rtems_unsigned8 unused_10;
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  rtems_unsigned8 utility_interrupt_vector;      /* 0xfffe2013 */
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  rtems_unsigned8 unused_11;
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  rtems_unsigned8 interrupt_request;             /* 0xfffe2015 */
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  rtems_unsigned8 unused_12;
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  rtems_unsigned8 vme_bus_status_id;             /* 0xfffe2017 */
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  rtems_unsigned8 unused_13;
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  rtems_unsigned8 bus_error_status;              /* 0xfffe2019 */
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  rtems_unsigned8 unused_14;
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  rtems_unsigned8 gcsr_base_address;             /* 0xfffe201b */
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};
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#define vme_lcsr      ((volatile struct vme_lcsr_map * const) 0xfffe2000)
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struct vme_gcsr_map {
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  rtems_unsigned8 unused_1;
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  rtems_unsigned8 global_0;                      /* 0xfffe2021 */
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  rtems_unsigned8 unused_2;
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  rtems_unsigned8 global_1;                      /* 0xfffe2023 */
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  rtems_unsigned8 unused_3;
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  rtems_unsigned8 board_identification;          /* 0xfffe2025 */
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  rtems_unsigned8 unused_4;
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  rtems_unsigned8 general_purpose_0;             /* 0xfffe2027 */
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  rtems_unsigned8 unused_5;
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  rtems_unsigned8 general_purpose_1;             /* 0xfffe2029 */
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  rtems_unsigned8 unused_6;
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  rtems_unsigned8 general_purpose_2;             /* 0xfffe202b */
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  rtems_unsigned8 unused_7;
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  rtems_unsigned8 general_purpose_3;             /* 0xfffe202d */
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  rtems_unsigned8 unused_8;
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  rtems_unsigned8 general_purpose_4;             /* 0xfffe202f */
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};
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#define vme_gcsr      ((volatile struct vme_gcsr_map * const) 0xfffe2020)
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#define z8530 0xfffe3001
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/* interrupt vectors - see MVME147/D1 4.14 */
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#define PCC_BASE_VECTOR        0x40 /* First user int */
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#define SCC_VECTOR             PCC_BASE_VECTOR+3
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#define TIMER_1_VECTOR         PCC_BASE_VECTOR+8
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#define TIMER_2_VECTOR         PCC_BASE_VECTOR+9  
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#define SOFT_1_VECTOR          PCC_BASE_VECTOR+10
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#define SOFT_2_VECTOR          PCC_BASE_VECTOR+11 
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#define VME_BASE_VECTOR        0x50
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#define VME_SIGLP_VECTOR       VME_BASE_VECTOR+1
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#define USE_CHANNEL_A   1                /* 1 = use channel A for console */
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#define USE_CHANNEL_B   0                /* 1 = use channel B for console */
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#if (USE_CHANNEL_A == 1)
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#define CONSOLE_CONTROL  0xfffe3002
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#define CONSOLE_DATA     0xfffe3003
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#elif (USE_CHANNEL_B == 1)
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#define CONSOLE_CONTROL  0xfffe3000
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#define CONSOLE_DATA     0xfffe3001
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#endif
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#define FOREVER       1                  /* infinite loop */
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#ifdef M147_INIT
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#undef EXTERN
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#define EXTERN
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#else
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#undef EXTERN
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#define EXTERN extern
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#endif
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/*
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 *  Define the time limits for RTEMS Test Suite test durations.
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 *  Long test and short test duration limits are provided.  These
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 *  values are in seconds and need to be converted to ticks for the
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 *  application.
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 *
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 */
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#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
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#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
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/*
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 *  Define the interrupt mechanism for Time Test 27
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 *
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 *  NOTE: Use the MPCSR vector for the MVME147
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 */
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208
#define MUST_WAIT_FOR_INTERRUPT 0
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#define Install_tm27_vector( handler ) set_vector( (handler), \
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                                                   SOFT_1_VECTOR, 1 )
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#define Cause_tm27_intr()  pcc->software_int_1_control = 0x0c
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  /* generate level 4 sotware int. */
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#define Clear_tm27_intr()  pcc->software_int_1_control = 0x00
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#define Lower_tm27_intr()
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/* miscellaneous stuff assumed to exist */
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extern rtems_configuration_table BSP_Configuration;
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225
extern m68k_isr_entry M68Kvec[];   /* vector table address */
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227
/*
228
 *  Device Driver Table Entries
229
 */
230
 
231
/*
232
 * NOTE: Use the standard Console driver entry
233
 */
234
 
235
/*
236
 * NOTE: Use the standard Clock driver entry
237
 */
238
 
239
/* functions */
240
 
241
void bsp_cleanup( void );
242
 
243
m68k_isr_entry set_vector(
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  rtems_isr_entry     handler,
245
  rtems_vector_number vector,
246
  int                 type
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);
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249
#ifdef __cplusplus
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}
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#endif
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#endif
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/* end of include file */
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