OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme147s/] [shmsupp/] [getcfg.c] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  void Shm_Get_configuration( localnode, &shmcfg )
2
 *
3
 *  This routine initializes, if necessary, and returns a pointer
4
 *  to the Shared Memory Configuration Table for the MVME147.
5
 *
6
 *  INPUT PARAMETERS:
7
 *    localnode - local node number
8
 *    shmcfg    - address of pointer to SHM Config Table
9
 *
10
 *  OUTPUT PARAMETERS:
11
 *    *shmcfg   - pointer to SHM Config Table
12
 *
13
 *  NOTES:  The SIGLP interrupt on the MVME147 is used as an interprocessor
14
 *          interrupt.
15
 *
16
 *  COPYRIGHT (c) 1989-1999.
17
 *  On-Line Applications Research Corporation (OAR).
18
 *
19
 *  The license and distribution terms for this file may be
20
 *  found in the file LICENSE in this distribution or at
21
 *  http://www.OARcorp.com/rtems/license.html.
22
 *
23
 *  MVME147 port for TNI - Telecom Bretagne
24
 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
25
 *  June 1996
26
 *
27
 *  $Id: getcfg.c,v 1.2 2001-09-27 12:00:17 chris Exp $
28
 */
29
 
30
#include <bsp.h>
31
#include <rtems.h>
32
#include "shm_driver.h"
33
 
34
#define INTERRUPT 1                   /* MVME147 target supports both */
35
#define POLLING   0                   /* polling and interrupt modes  */
36
 
37
shm_config_table BSP_shm_cfgtbl;
38
 
39
rtems_unsigned32 *BSP_int_address()
40
{
41
  rtems_unsigned32 id, offset;
42
 
43
  id      = (rtems_unsigned32) vme_lcsr->gcsr_base_address;
44
  offset  = (id << 4) & 0xF0;
45
  offset |= 0xffff0003; /* points to GCSR global 1 */
46
  return( (rtems_unsigned32 * ) offset );
47
}
48
 
49
void Shm_Get_configuration(
50
  rtems_unsigned32   localnode,
51
  shm_config_table **shmcfg
52
)
53
{
54
  /* A shared mem space has bee left between RAM_END and DRAM_END
55
   on the first node*/
56
  if (localnode == 1)
57
    BSP_shm_cfgtbl.base       = (vol_u32 *) RAM_END;
58
  else
59
    BSP_shm_cfgtbl.base       = (vol_u32 *) (DRAM_END + RAM_END);
60
 
61
  BSP_shm_cfgtbl.length       = DRAM_END - RAM_END;
62
  BSP_shm_cfgtbl.format       = SHM_BIG;
63
 
64
  BSP_shm_cfgtbl.cause_intr   = Shm_Cause_interrupt;
65
 
66
#ifdef NEUTRAL_BIG
67
  BSP_shm_cfgtbl.convert      = NULL_CONVERT;
68
#else
69
  BSP_shm_cfgtbl.convert      = CPU_swap_u32;
70
#endif
71
 
72
#if (POLLING==1)
73
  BSP_shm_cfgtbl.poll_intr    = POLLED_MODE;
74
  BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT;
75
  BSP_shm_cfgtbl.Intr.value   = NO_INTERRUPT;
76
  BSP_shm_cfgtbl.Intr.length  = NO_INTERRUPT;
77
#else
78
  BSP_shm_cfgtbl.poll_intr    = INTR_MODE;
79
  BSP_shm_cfgtbl.Intr.address = BSP_int_address(); /* GCSR global 1 */
80
  BSP_shm_cfgtbl.Intr.value   = 0x01; /* SIGLP */
81
  BSP_shm_cfgtbl.Intr.length  = BYTE;
82
#endif
83
 
84
  *shmcfg = &BSP_shm_cfgtbl;
85
 
86
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.