OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [mvme162/] [startup/] [page_table.c] - Blame information for rev 593

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  $Id: page_table.c,v 1.2 2001-09-27 12:00:18 chris Exp $
3
 *
4
 *  This file was submitted by Eric Vaitl <vaitl@viasat.com>.
5
 *  The manipulation of the page table has a very positive impact on
6
 *  the performance of the MVME162.
7
 *
8
 *  The following history is included verbatim from the submitter.
9
 *
10
 * Revision 1.8  1995/11/18  00:07:25  vaitl
11
 * Modified asm statements to get rid of the register hard-codes.
12
 *
13
 * Revision 1.7  1995/10/27  21:00:32  vaitl
14
 * Modified page table routines so application code can map
15
 * VME space.
16
 *
17
 * Revision 1.6  1995/10/26  17:40:01  vaitl
18
 * Two cache changes after reading the mvme162 users manual.
19
 *
20
 * 1) The users manual says that the MPU can act as a source for the
21
 *    VME2 chip, so I made the VME accessable memory copy-back instead
22
 *    of write through.  I have't changed the comments yet. If this
23
 *    causes problems, I'll change it back.
24
 *
25
 * 2) The 162 book also says that IO space should be serialized as well as
26
 *    non-cacheable. I flipped the appropriate dttr0 and ittr0 registers. I
27
 *    don't think this is really necessary because we don't recover from any
28
 *    exceptions. If it slows down IO addresses too much, I'll change it back
29
 *    and see what happens.
30
 *
31
 * Revision 1.5  1995/10/25  19:32:38  vaitl
32
 * Got it. Three problems:
33
 *   1) Must cpusha instead of cinva.
34
 *   2) On page descriptors the PDT field of 1 or 3 is resident. On pointer
35
 *      descriptors resident is 2 or 3. I was using 2 for everything.
36
 *      Changed it to 3 for everything.
37
 *   3) Forgot to do a pflusha.
38
 *
39
 * Revision 1.4  1995/10/25  17:47:11  vaitl
40
 * Still working on it.
41
 *
42
 * Revision 1.3  1995/10/25  17:16:05  vaitl
43
 * Working on page table. Caching partially set up, but can't currently
44
 * set tc register.
45
 *
46
 */
47
 
48
#include <string.h>
49
#include <page_table.h>
50
 
51
/* All page table must fit between BASE_TABLE_ADDR and
52
   MAX_TABLE_ADDR. */
53
 
54
#define BASE_TABLE_ADDR 0x10000
55
#define MAX_TABLE_ADDR 0x20000
56
#define ROOT_TABLE_SIZE 512
57
#define POINTER_TABLE_SIZE 512
58
#define PAGE_TABLE_SIZE 256
59
 
60
static unsigned long *root_table;
61
static unsigned long *next_avail;
62
 
63
/* Returns a zeroed out table. */
64
static unsigned long *table_alloc(int size){
65
    unsigned long *addr=next_avail;
66
    if(((unsigned long)next_avail + size) > MAX_TABLE_ADDR){
67
        return 0;
68
    }
69
    bzero((void *)addr,size);
70
    next_avail =(unsigned long *)((unsigned long)next_avail + size);
71
    return addr;
72
}
73
 
74
 
75
 
76
/*
77
   void page_table_init();
78
 
79
   This should transparently map the first 4 Meg of ram.  Caching is
80
   turned off from 0x00000000 to 0x00020000 (this region is used by
81
   162Bug and contains the page tables). From 0x00020000 to 0x00400000
82
   we are using copy back caching. DTTR0 and ITTR0 are set up to
83
   directly translate from 0x80000000-0xffffffff with caching turned
84
   off and serialized. Addresses between 0x400000 and 0x80000000 are
85
   illegal.
86
*/
87
void page_table_init(){
88
 
89
    /* put everything in a known state */
90
    page_table_teardown();
91
 
92
    root_table=table_alloc(ROOT_TABLE_SIZE);
93
 
94
    /* First set up TTR.
95
       base address = 0x80000000
96
       address mask = 0x7f
97
       Ignore FC2 for match.
98
       Noncachable.
99
       Not write protected.*/
100
    asm volatile ("movec %0,%%dtt0
101
                   movec %0,%%itt0"
102
                  :: "d" (0x807fc040));
103
 
104
    /* Point urp and srp at root page table. */
105
    asm volatile ("movec %0,%%urp
106
                   movec %0,%%srp"
107
                  :: "d" (BASE_TABLE_ADDR));
108
 
109
    page_table_map((void *)0,0x20000, CACHE_NONE);
110
    page_table_map((void *)0x20000,0x400000-0x20000,CACHE_COPYBACK);
111
 
112
    /* Turn on paging with a 4 k page size.*/
113
    asm volatile ("movec %0,%%tc"
114
                  :: "d" (0x8000));
115
 
116
    /* Turn on the cache. */
117
    asm volatile ("movec %0,%%cacr"
118
                  :: "d" (0x80008000));
119
}
120
 
121
void page_table_teardown(){
122
    next_avail=(unsigned long *)BASE_TABLE_ADDR;
123
    /* Turn off paging.  Turn off the cache. Flush the cache. Tear down
124
       the transparent translations. */
125
    asm volatile ("movec %0,%%tc
126
                   movec %0,%%cacr
127
                   cpusha %%bc
128
                   movec %0,%%dtt0
129
                   movec %0,%%itt0
130
                   movec %0,%%dtt1
131
                   movec %0,%%itt1"
132
                  :: "d" (0) );
133
}
134
 
135
/* Identity maps addr to addr+size with caching cache_type. */
136
int page_table_map(void *addr, unsigned long size, int cache_type){
137
    unsigned long *pointer_table;
138
    unsigned long *page_table;
139
    unsigned long root_index, pointer_index, page_index;
140
    /* addr must be a multiple of 4k */
141
    if((unsigned long)addr & 0xfff){
142
        return  PTM_BAD_ADDR;
143
    }
144
    /* size must also be a multiple of 4k */
145
    if(size & 0xfff){
146
        return PTM_BAD_SIZE;
147
    }
148
    /* check for valid cache type */
149
    if( (cache_type>CACHE_NONE) || (cache_type<CACHE_WRITE_THROUGH)){
150
        return PTM_BAD_CACHE;
151
    }
152
 
153
    while(size){
154
        root_index=(unsigned long)addr;
155
        root_index >>= 25;
156
        root_index &= 0x7f;
157
 
158
        if(root_table[root_index]){
159
            pointer_table =
160
                (unsigned long *) (root_table[root_index] & 0xfffffe00);
161
        }else{
162
            if(!(pointer_table=table_alloc(POINTER_TABLE_SIZE))){
163
                return  PTM_NO_TABLE_SPACE;
164
            }
165
            root_table[root_index]=((unsigned long)pointer_table) + 0x03;
166
        }
167
 
168
        pointer_index=(unsigned long)addr;
169
        pointer_index >>=18;
170
        pointer_index &= 0x7f;
171
 
172
        if(pointer_table[pointer_index]){
173
            page_table =
174
                (unsigned long *) (pointer_table[pointer_index] &
175
                                   0xffffff00);
176
        }else{
177
            if(!(page_table=table_alloc(PAGE_TABLE_SIZE))){
178
                return  PTM_NO_TABLE_SPACE;
179
            }
180
            pointer_table[pointer_index]=
181
                ((unsigned long)page_table) + 0x03;
182
        }
183
 
184
        page_index=(unsigned long)addr;
185
        page_index >>=12;
186
        page_index &= 0x3f;
187
 
188
        page_table[page_index] =
189
            ((unsigned long) addr & 0xfffff000) + 0x03 + (cache_type << 5);
190
 
191
        size -= 4096;
192
        addr = (void *) ((unsigned long)addr + 4096);
193
    }
194
 
195
    /* Flush the ATC. Push and invalidate the cache. */
196
    asm volatile ("pflusha
197
                   cpusha %bc");
198
 
199
    return  PTM_SUCCESS;
200
}
201
 
202
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.