OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [ods68302/] [startup/] [rom] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 * $Id: rom,v 1.2 2001-09-27 12:00:23 chris Exp $
3
 *
4
 * MC68302 Linker command file
5
 *
6
 */
7
 
8
SECTIONS
9
{
10
  .text . :
11
  {
12
    text_start = .;
13
    *(.text)
14
    etext = .;
15
    . = ALIGN(4);
16
    __CTOR_LIST__ = .;
17
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
18
    *(.ctors)
19
    LONG(0)
20
    __CTOR_END__ = .;
21
    . = ALIGN(4);
22
    __DTOR_LIST__ = .;
23
    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
24
    *(.dtors)
25
    LONG(0)
26
    __DTOR_END__ = .;
27
  }
28
 
29
  .vtable 0 :
30
  {
31
    vtable_start = .;
32
    *(.vtable)
33
    evtable = .;
34
  }
35
 
36
  .data (ADDR(.vtable) + SIZEOF(.vtable)) :
37
     AT (ADDR(.text) + SIZEOF(.text))
38
  {
39
    data_start = .;
40
    *(.data)
41
    edata = .;
42
  }
43
  .bss (ADDR(.data) + SIZEOF(.data)) :
44
  {
45
    bss_start = .;
46
    *(.bss)
47
    *(COMMON)
48
    end = . ;
49
    _end = . ;
50
  }
51
}
52
 
53
m302 = MC68302_BASE;
54
_VBR = 0;               /* location of the VBR table (in RAM) */
55
 
56
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.