OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [ods68302/] [startup/] [trace.c] - Blame information for rev 593

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*****************************************************************************/
2
/*
3
  $Id: trace.c,v 1.2 2001-09-27 12:00:23 chris Exp $
4
 
5
  Trace Exception dumps a back trace to the debug serial port
6
 
7
 */
8
/*****************************************************************************/
9
 
10
#include <bsp.h>
11
#include <debugport.h>
12
 
13
#if 0
14
/* FIXME : could get the string to print when in the BSP */
15
static const char *exception_names[] =
16
{
17
  "RESET STACK TOP",
18
  "RESET",
19
  "BUS ERROR",
20
  "ADDRESS ERROR",
21
  "ILLEGAL OPCODE",
22
  "ZERO DIVIDE",
23
  "CHK",
24
  "OVERFLOW",
25
  "PRIVILEGE",
26
  "TRACE",
27
  "LINE 1010 EMULATOR",
28
  "LINE 1111 EMULATOR",
29
  "UNASSIGNED 12",
30
  "UNASSIGNED 13",
31
  "FORMAT ERROR",
32
  "UNINITIALISED INTERRUPT",
33
  "UNASSIGNED 16",
34
  "NODE ANCHOR",
35
  "SYSTEM ANCHOR",
36
  "UNASSIGNED 19",
37
  "UNASSIGNED 20",
38
  "UNASSIGNED 21",
39
  "UNASSIGNED 22",
40
  "UNASSIGNED 23",
41
  "SPURIOUS HANDLER",
42
  "LEVEL 1",
43
  "LEVEL 2",
44
  "LEVEL 3",
45
  "LEVEL 4",
46
  "LEVEL 5",
47
  "LEVEL 6",
48
  "LEVEL 7",
49
  "TRAP 0",
50
  "TRAP 1",
51
  "TRAP 2",
52
  "TRAP 3",
53
  "TRAP 4",
54
  "TRAP 5",
55
  "TRAP 6",
56
  "TRAP 7",
57
  "TRAP 8",
58
  "TRAP 9",
59
  "TRAP 10",
60
  "TRAP 11",
61
  "TRAP 12",
62
  "TRAP 13",
63
  "TRAP 14",
64
  "TRAP 15"
65
};
66
#endif
67
 
68
void trace_exception(unsigned long d0,
69
                     unsigned long d1,
70
                     unsigned long d2,
71
                     unsigned long d3,
72
                     unsigned long d4,
73
                     unsigned long d5,
74
                     unsigned long d6,
75
                     unsigned long d7,
76
                     unsigned long a0,
77
                     unsigned long a1,
78
                     unsigned long a2,
79
                     unsigned long a3,
80
                     unsigned long a4,
81
                     unsigned long a5,
82
                     unsigned long a6,
83
                     unsigned long a7,
84
                     unsigned long sr_pch,
85
                     unsigned long pcl_format)
86
{
87
  unsigned int sr = sr_pch >> 16;
88
  unsigned long pc = (sr_pch << 16) | (pcl_format >> 16);
89
  unsigned int format = pcl_format & 0xFFFF;
90
  unsigned int index;
91
  unsigned char ch;
92
 
93
  asm volatile(" orw #0x0700,%sr");
94
 
95
  debug_port_banner();
96
 
97
  debug_port_write("unhandled exception=");
98
  debug_port_write_hex_uint(format >> 2);
99
  debug_port_write("\n");
100
 
101
  debug_port_write("sr=");
102
  debug_port_write_hex_uint(sr);
103
  debug_port_write(", pc=");
104
  debug_port_write_hex_ulong(pc);
105
  debug_port_write("\n");
106
 
107
  for (index = 0; index < 16; index++)
108
  {
109
    if (index == 8)
110
    {
111
      debug_port_write("\n\r");
112
    }
113
    if (index < 8)
114
    {
115
      debug_port_out('d');
116
      debug_port_out('0' + index);
117
    }
118
    else
119
    {
120
      debug_port_out('a');
121
      debug_port_out('0' + index - 8);
122
    }
123
    debug_port_out('=');
124
    debug_port_write_hex_ulong(*(((unsigned long*) &d0) + index));
125
    debug_port_out(' ');
126
  }
127
 
128
  for (index = 0; index < (16 * 10); index++)
129
  {
130
    if ((index % 16) == 0)
131
    {
132
      debug_port_write("\n");
133
      debug_port_write_hex_ulong((unsigned long) (((char*) &index) + index));
134
      debug_port_write(" : ");
135
    }
136
    else
137
    {
138
      debug_port_out(' ');
139
    }
140
 
141
    ch = (*(((char*) &index) + index) >> 4) & 0x0F;
142
 
143
    if (ch < 10)
144
    {
145
      ch += '0';
146
    }
147
    else
148
    {
149
      ch += 'a' - 10;
150
    }
151
 
152
    debug_port_out((char) ch);
153
 
154
    ch = *(((char*) &index) + index) & 0x0F;
155
 
156
    if (ch < 10)
157
    {
158
      ch += '0';
159
    }
160
    else
161
    {
162
      ch += 'a' - 10;
163
    }
164
    debug_port_out((char) ch);
165
  }
166
 
167
  debug_port_write("\nhalting cpu...");
168
 
169
#if defined(UPDATE_DISPLAY)
170
  UPDATE_DISPLAY("HALT");
171
#endif
172
 
173
  WATCHDOG_TRIGGER();
174
  while (1 == 1);
175
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.