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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [ods68302/] [timer/] [timerisr.S] - Blame information for rev 30

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1 30 unneback
/*
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 * Handle 68302 TIMER2 interrupts.
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 *
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 * All code in this routine is pure overhead which can perturb the
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 * accuracy of RTEMS' timing test suite.
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 *
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 * See also:    Read_timer()
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 *
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 * To reduce overhead this is best to be the "rawest" hardware interupt
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 * handler you can write.  This should be the only interrupt which can
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 * occur during the measured time period.
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 *
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 * An external counter, Timer_interrupts, is incremented.
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 *
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 *  $Id: timerisr.S,v 1.2 2001-09-27 12:00:23 chris Exp $
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 */
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#include "asm.h"
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BEGIN_CODE
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        PUBLIC(timerisr)
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SYM(timerisr):
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        move.w  #0x0040,SYM(m302)+2072  | clear interrupt in-service bit
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        move.b  #3,SYM(m302)+2137       | clear timer interrupt event register
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        addq.l  #1,SYM(Timer_interrupts) | increment timer value
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        rte
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END_CODE
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END

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