OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [shared/] [setvec.c] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *
3
 *  This routine installs an interrupt vector using the basic
4
 *  RTEMS mechanisms.  This implementation should be suitable for
5
 *  most m68k based boards.  However, if the board has an unusual
6
 *  interrupt controller or most somehow manipulate board specific
7
 *  hardware to enable/disable, mask, prioritize, etc an interrupt
8
 *  source, then this routine should be customized to support that.
9
 *
10
 *  COPYRIGHT (c) 1989-1999.
11
 *  On-Line Applications Research Corporation (OAR).
12
 *
13
 *  The license and distribution terms for this file may be
14
 *  found in the file LICENSE in this distribution or at
15
 *  http://www.OARcorp.com/rtems/license.html.
16
 *
17
 *  $Id: setvec.c,v 1.2 2001-09-27 12:00:24 chris Exp $
18
 */
19
 
20
#include <rtems.h>
21
#include <bsp.h>
22
 
23
m68k_isr_entry set_vector(                      /* returns old vector */
24
  rtems_isr_entry     handler,                  /* isr routine        */
25
  rtems_vector_number vector,                   /* vector number      */
26
  int                 type                      /* RTEMS or RAW intr  */
27
)
28
{
29
  m68k_isr_entry  previous_isr;
30
 
31
  if ( type )
32
    rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
33
  else {
34
    _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
35
  }
36
  return previous_isr;
37
}
38
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.