OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [m68k/] [shared/] [start.S] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*  entry.s
2
 *
3
 *  This file contains the entry point for the application.
4
 *  The name of this entry point is compiler dependent.
5
 *  It jumps to the BSP which is responsible for performing
6
 *  all initialization.
7
 *
8
 *  COPYRIGHT (c) 1989-1999.
9
 *  On-Line Applications Research Corporation (OAR).
10
 *
11
 *  The license and distribution terms for this file may be
12
 *  found in the file LICENSE in this distribution or at
13
 *  http://www.OARcorp.com/rtems/license.html.
14
 *
15
 *  $Id: start.S,v 1.2 2001-09-27 12:00:24 chris Exp $
16
 */
17
 
18
#include "asm.h"
19
 
20
#if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */
21
 
22
BEGIN_CODE
23
                                        | Default entry points for:
24
         PUBLIC (start)                 |   GNU
25
         PUBLIC (M68Kvec)               |   Vector Table
26
 
27
SYM (start):
28
SYM (M68Kvec):                          | standard location for vectors
29
        nop                             | for linkers with problem
30
                                        | location zero
31
        jmp      SYM (start_around)
32
 
33
     /*
34
      *  We can use the following space as our vector table
35
      *  if the CPU has a VBR or we can save vector table in it
36
      *  if the CPU does not.
37
      */
38
 
39
        .space   4088                   | to avoid initial intr stack
40
                                        |   from 135BUG on MVME13?
41
                                        |   and start code at 0x4000
42
SYM (vectors):
43
        .space   1016                   | reserve space for rest of vectors
44
 
45
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
46
SYM (lowintstack):
47
        .space   4092                   | reserve for interrupt stack
48
SYM (hiintstack):
49
        .space   4                      | end of interrupt stack
50
#endif
51
 
52
        PUBLIC (start_around)
53
SYM (start_around):
54
        move.w  sr, SYM (initial_sr)
55
        oriw    #0x3700,sr              | SUPV MODE,INTERRUPTS OFF!!!
56
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
57
        movec   isp,a0
58
        move.l  a0, SYM (initial_isp)
59
        movec   usp,a0
60
        move.l  a0, SYM (initial_usp)
61
        movec   msp,a0
62
        move.l  a0, SYM (initial_msp)
63
#else
64
        move.l  a7, SYM (initial_msp)
65
#endif
66
 
67
        |
68
        | zero out uninitialized data area
69
        |
70
zerobss:
71
        moveal  # SYM (_clear_end),a0     | find end of .bss
72
        moveal  # SYM (_clear_start),a1   | find beginning of .bss
73
        movel   #0,d0
74
 
75
loop:   movel   #0,a1@+                 | to zero out uninitialized
76
        cmpal   a0,a1
77
        jlt     loop                    | loop until _end reached
78
 
79
        movel   # SYM (_stack_init),d0  | d0 = stop of stack
80
        movw    #0x3700,sr              | SUPV MODE,INTERRUPTS OFF!!!
81
        movel   d0,a7                   | set master stack pointer
82
        movel   d0,a6                   | set base pointer
83
 
84
      /*
85
       *  RTEMS should maintain a separate interrupt stack on CPUs
86
       *  without one in hardware.  This is currently not supported
87
       *  on versions of the m68k without a HW intr stack.
88
       */
89
 
90
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
91
        lea     SYM (hiintstack),a0   | a0 = high end of intr stack
92
        movec   a0,isp                | set interrupt stack
93
#endif
94
        pea     env                   | push environp
95
        pea     arg                   | push argv
96
        movel   #0,a7@-               | push argc
97
 
98
        jsr     SYM (boot_card)
99
        addl    #12,a7
100
 
101
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
102
        move.l  SYM (initial_isp),a0
103
        movec   a0,isp
104
        move.l  SYM (initial_usp),a0
105
        movec   a0,usp
106
        move.l  SYM (initial_msp),a0
107
        movec   a0,msp
108
#else
109
        movea.l SYM (initial_msp),a7
110
#endif
111
        move.w  SYM (initial_sr),sr
112
        rts
113
 
114
END_CODE
115
 
116
BEGIN_DATA
117
 
118
        PUBLIC (environ)
119
        .align 2
120
SYM (environ):
121
        .long   env
122
 
123
        PUBLIC (start_frame)
124
SYM (start_frame):
125
        .space  4,0
126
 
127
END_DATA
128
 
129
BEGIN_BSS
130
 
131
env: .long  0
132
arg: .long  0
133
 
134
        PUBLIC (initial_isp)
135
SYM (initial_isp):
136
        .space  4
137
 
138
        PUBLIC (initial_msp)
139
SYM (initial_msp):
140
        .space  4
141
 
142
        PUBLIC (initial_usp)
143
SYM (initial_usp):
144
        .space  4
145
 
146
         PUBLIC (initial_sr)
147
SYM (initial_sr):
148
        .space  2
149
 
150
END_DATA
151
#endif
152
END
153
 
154
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.