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/* start.S -- bootup code for the Bender board using the Or1k
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* architecture.
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*
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* Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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*
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* This file is distributed as part of the RTEMS package from
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* OAR Corporation, and follows the licensing and distribution
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* terms as stated for RTEMS.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*/
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#include "asm.h"
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/* Since we don't yet have a memory map for Bender, I am
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assuming the following. Hopefully, this will be easily
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modified once we get the real values.
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0x00000000 - 0x00200000: Flash/ROM (boot code / 2 MB)
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0x01000000 - 0x010FFFFF: Synchronous SRAM (area 2 / 1 MB)
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0x10000000 - 0x1FFFFFFF: External SDRAM (area 3 / 256 MB)
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0x20000000 - 0x2FFFFFFF: External SDRAM (area 4 / 256 MB)
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0x80000000 - 0x8000001F: 4 16550 UART controllers
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0x80010000 - 0x80017FFF: Internal Bender RAM
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0x80020000 - 0xFFFFFFFF: Memory mapped Bender Peripherals
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For this version, I assume that only the flash and 32 MB
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of RAM in area 3 are populated. Everything else should
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return a bus error when accessed.
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*/
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.file "start.S"
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.data
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PUBLIC(Or1k_Interrupt_Vectors)
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SYM (Or1k_Interrupt_Vectors):
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.word 0x00000000 # No Vector
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.word _start # Reset Vector (Ignored)
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.word __Internal_error_Occurred # Bus Error
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.word __Internal_error_Occurred # Data Page Fault
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.word __Internal_error_Occurred # Instruction Page Fault
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.word __int_reenable # Low Priority Interrupt
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.word __Internal_error_Occurred # Alignment Exception
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.word __Internal_error_Occurred # Illegal Instruction Exception
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.word __int_reenable # High Priority Interrupt
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.word __Internal_error_Occurred # ITBL Miss
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.word __Internal_error_Occurred # DTBL Miss
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.word 0x00000000 # Range Exception
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.word 0x00000000 # System Call
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.word 0x00000000 # Breakpoint
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.word 0x00000000 # Trap
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/*
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PUBLIC(BOTTOM_OF_MEMORY)
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SYM (BOTTOM_OF_MEMORY):
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.word 0x10000000 # Assume RAM @ 0 for the sim
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PUBLIC(TOP_OF_MEMORY)
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SYM (TOP_OF_MEMORY):
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.word 0x10800000 # Assume RAM @ 0 for the sim
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*/
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PUBLIC(_mem_end)
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SYM (_mem_end):
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.word 0x10800000
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BEGIN_CODE
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.org 0x0
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/**************/
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/* _panic */
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/**************/
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/* Place the panic vector at 0 */
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.proc __panic
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.def __panic
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.val __panic
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.scl 2
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.type 044
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.endef
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.global __panic
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__panic:
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l.jal __exit
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l.nop
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.endproc __panic
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.def __panic
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.val .
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.scl -1
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.endef
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/* Exception processing...first, we will save the
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16 non callee saved registers which could be
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corrupted by calling a C function. We have no
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way of knowing which of these will be used, so
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we have to save all of them. We will then save
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the EPCR and ESR, in case a nested exception is
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called. Next, we call the user function. We then
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restore all the registers to their original
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values, and finally disable exceptions, restore
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EPCR and ESR (EEAR is not essential to restore)
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and then return from the interrupt. */
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/******************************************/
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/* Normal exception handling */
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/* Called with 80 bytes allocated on the */
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/* stack, the vector function in r11, and */
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/* the vector number in r3. Original */
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/* values at 28(r1) and 0(r1). */
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/******************************************/
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.proc ___standard_exception
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.def ___standard_exception
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.val ___standard_exception
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.scl 2
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.type 044
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.endef
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.global ___standard_exception
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___standard_exception:
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l.sfeqi r11,0 /* Ignore it if it is zero */
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l.bf L2_2
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l.sw 4(r1),r4 /* Save r4 */
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/* Ignore fast context switching in this release. */
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/* It's poorly conceived, and will probably never */
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/* be implemented... */
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l.sw 8(r1),r5
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l.sw 12(r1),r6
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l.sw 16(r1),r7
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l.mfspr r4,r0,0x20 /* Save EPCR */
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l.mfspr r5,r0,0x30 /* Save EEAR */
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l.mfspr r6,r0,0x40 /* Save ESR */
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l.mfspr r7,r0,17
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l.ori r7,r7,2
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l.mtspr r0,r7,17 /* Reenable exceptions */
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l.sw 20(r1),r8
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l.sw 24(r1),r9
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l.sw 32(r1),r12
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l.sw 36(r1),r14
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l.sw 40(r1),r16
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l.sw 44(r1),r18
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l.sw 48(r1),r20
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l.sw 52(r1),r22
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l.sw 56(r1),r24
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l.sw 60(r1),r26
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l.sw 64(r1),r28
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l.sw 68(r1),r30
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l.sw 72(r1),r4 /* Save EPCR. User could change r4 */
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/* Now, call the installed handler with the arguments:
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r3 ==> vector # (1-14)
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r4 ==> EPCR
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r5 ==> EEAR
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r6 ==> ESR
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r11 ==> User function
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*/
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l.jal ___user_function /* Call the user routine */
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l.sw 76(r1),r6 /* Save ESR. User could change r6 */
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/* Ignore r5 (EEAR). It is not critical for state */
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l.lwz r30,68(r1)
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l.lwz r28,64(r1)
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l.lwz r26,60(r1)
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l.lwz r24,56(r1)
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l.lwz r22,52(r1)
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l.lwz r20,48(r1)
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l.lwz r18,44(r1)
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l.lwz r16,40(r1)
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l.lwz r14,36(r1)
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l.lwz r12,32(r1)
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l.lwz r9,24(r1)
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l.lwz r8,20(r1)
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l.lwz r7,16(r1)
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l.lwz r5,8(r1)
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l.addi r6,r0,-3 /* Set r6 to 0xFFFFFFFD */
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l.mfspr r3,r0,17 /* Get SR value */
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l.and r3,r3,r6 /* Clear exception bit */
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l.mfspr r0,r3,17 /* Disable exceptions */
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l.lwz r6,76(r1) /* Recover ESR */
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l.lwz r4,72(r1) /* Recover EPCR */
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l.mtspr r0,r4,0x20 /* Restore ESR */
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l.mtspr r0,r6,0x40 /* Restore EPCR */
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l.lwz r6,12(r1)
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l.lwz r4,4(r1)
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L2_2:
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l.lwz r11,28(r1)
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l.lwz r3,0(r1)
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l.addi r1,r1,80
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l.rfe
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l.nop /* The document doesn't say this is
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a delay slot instruction, but the
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simulator doesn't work without this. */
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.endproc ___standard_exception
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.def ___standard_exception
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.val .
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.scl -1
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.endef
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/****************************************************************************/
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/* These constants must be in .text section in order to be */
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/* properly addressed in code. */
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PUBLIC(BOTTOM_OF_MEMORY)
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SYM (BOTTOM_OF_MEMORY):
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.word 0x10000000 # Assume RAM @ 0 for the sim
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PUBLIC(TOP_OF_MEMORY)
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SYM (TOP_OF_MEMORY):
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.word 0x10800000 # Assume RAM @ 0 for the sim
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/****************************************************************************/
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/** Currently, about 57 of the 64 valid address locations
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are being used here. If you add code to the above
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routine, make sure it isn't more than 7 instructions
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or you will overflow into the reset vector. **/
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/****************************/
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/* Reset vector static code */
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/****************************/
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.org 0x100
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.proc ___rst
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| 238 |
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.global ___rst
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___rst:
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/* Set the stack pointer */
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l.movhi r1,hi(_TOP_OF_MEMORY)
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l.ori r1,r1,lo(_TOP_OF_MEMORY)
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l.lwz r1,0(r1) /* Dereference it */
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/* Set the frame pointer */
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| 246 |
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l.add r2,r0,r1
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| 248 |
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l.mfspr r3,r0,17 /* Get SR value */
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| 249 |
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l.ori r3,r3,2 /* Set exception enable bit */
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l.j _start /* Jump to main routine */
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| 251 |
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l.mtspr r0,r3,17 /* Enable exceptions (DELAY) */
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.endproc ___rst
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| 253 |
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| 254 |
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/***********************************************************/
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| 255 |
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/* Note: right after the reset vector, we are going to */
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| 256 |
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/* place a table with the necessary values to initialize */
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| 257 |
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/* the memory controller. This pointer will be set and */
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| 258 |
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/* passed to the _start routine in r4. The first thing the */
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| 259 |
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/* the _start routine will do is to initialize the memory */
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| 260 |
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/* controller. The code to initialze the memory controller */
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| 261 |
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/* is expected to be larger than the 50 some odd */
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| 262 |
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/* instructions that are remaining here before the bus */
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| 263 |
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/* error vector, which is why it is left to the _start */
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/* routine. */
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| 265 |
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/***********************************************************/
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| 266 |
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| 267 |
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/********************************/
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| 268 |
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/* Bus Error vector static code */
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| 269 |
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/********************************/
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| 270 |
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.org 0x200
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| 271 |
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.proc ___bus_error
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.global ___bus_error
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___bus_error:
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| 274 |
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l.addi r1,r1,-80
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| 275 |
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l.sw 0(r1),r3
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| 276 |
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l.sw 28(r1),r11
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l.movhi r11,hi(_Or1k_Interrupt_Vectors)
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| 278 |
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l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
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| 279 |
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l.lwz r11,8(r11)
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| 280 |
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l.j ___standard_exception
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| 281 |
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l.addi r3,r0,2
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| 282 |
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| 283 |
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.endproc ___bus_error
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| 284 |
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| 285 |
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/* Put _Internal_error_Occurred and _int_reenable here */
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| 286 |
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/* No reason to waste space...it'll be filled with 0 if */
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| 287 |
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/* we don't... */
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| 288 |
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| 289 |
|
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/********************************/
|
| 290 |
|
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/* _Internal_error_Occurred */
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| 291 |
|
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/********************************/
|
| 292 |
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|
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| 293 |
|
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.proc __Internal_error_Occurred
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| 294 |
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.def __Internal_error_Occurred
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| 295 |
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.val __Internal_error_Occurred
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| 296 |
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.scl 2
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| 297 |
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.type 044
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| 298 |
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.endef
|
| 299 |
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.global __Internal_error_Occurred
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| 300 |
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__Internal_error_Occurred:
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| 301 |
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| 302 |
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l.jal __panic
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| 303 |
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l.nop
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| 304 |
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| 305 |
|
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.endproc __Internal_error_Occurred
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| 306 |
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.def __Internal_error_Occurred
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| 307 |
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.val .
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| 308 |
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.scl -1
|
| 309 |
|
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.endef
|
| 310 |
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| 311 |
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| 312 |
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/*********************/
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| 313 |
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/* _int_reenable */
|
| 314 |
|
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/*********************/
|
| 315 |
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| 316 |
|
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.proc __int_reenable
|
| 317 |
|
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.def __int_reenable
|
| 318 |
|
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.val __int_reenable
|
| 319 |
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.scl 2
|
| 320 |
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.type 044
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| 321 |
|
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.endef
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| 322 |
|
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.global __int_reenable
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| 323 |
|
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__int_reenable:
|
| 324 |
|
|
|
| 325 |
|
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l.mfspr r11,r0,17
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| 326 |
|
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l.ori r11,r11,0x04
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| 327 |
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l.jr r9
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| 328 |
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l.mtspr r0,r11,17
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| 329 |
|
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|
| 330 |
|
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.endproc __int_reenable
|
| 331 |
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.def __int_reenable
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| 332 |
|
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.val .
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| 333 |
|
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.scl -1
|
| 334 |
|
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.endef
|
| 335 |
|
|
|
| 336 |
|
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/*********************&**/
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| 337 |
|
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/* ___user_function */
|
| 338 |
|
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/************************/
|
| 339 |
|
|
|
| 340 |
|
|
.proc ___user_function
|
| 341 |
|
|
.def ___user_function
|
| 342 |
|
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.val ___user_function
|
| 343 |
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.scl 2
|
| 344 |
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.type 044
|
| 345 |
|
|
.endef
|
| 346 |
|
|
.global ___user_function
|
| 347 |
|
|
___user_function:
|
| 348 |
|
|
|
| 349 |
|
|
/* r11 contains the address to call. We can
|
| 350 |
|
|
modify r7, r8, r12, and r14 at will */
|
| 351 |
|
|
|
| 352 |
|
|
l.movhi r7,hi(__Thread_Dispatch_disable_level)
|
| 353 |
|
|
l.ori r7,r7,lo(__Thread_Dispatch_disable_level)
|
| 354 |
|
|
l.lwz r8,0(r7)
|
| 355 |
|
|
|
| 356 |
|
|
l.addi r1,r1,-8 # Stack must be DWORD aligned
|
| 357 |
|
|
l.sw 0(r1),r9 # Save the return address
|
| 358 |
|
|
|
| 359 |
|
|
l.addi r8,r8,1 # Increment __Thread_Dispatch...
|
| 360 |
|
|
l.jalr r11
|
| 361 |
|
|
l.sw 0(r7),r8 # Disable thread dispatching
|
| 362 |
|
|
|
| 363 |
|
|
/* Now, we need to determine if we need to
|
| 364 |
|
|
service the RTEMS environment. RTEMS tries
|
| 365 |
|
|
to draw a distinction between a RAW handler
|
| 366 |
|
|
(where this isn't necessary) and an RTEMS
|
| 367 |
|
|
handler. However, it appears almost all ISR's
|
| 368 |
|
|
will not be RAW under this definition, and
|
| 369 |
|
|
those that are will not honestly be hurt by
|
| 370 |
|
|
the 20 or so extra cycles it will take to do
|
| 371 |
|
|
the following code. If there is a very frequent
|
| 372 |
|
|
interrupt, then it should probably be hard
|
| 373 |
|
|
coded into the static routine anyway, rather
|
| 374 |
|
|
than suffer the hit of calling it indirectly */
|
| 375 |
|
|
|
| 376 |
|
|
/* Note: RTEMS recommends incrementing and
|
| 377 |
|
|
decrementing the _ISR_Nest_Level as well.
|
| 378 |
|
|
We are specifically not doing this because
|
| 379 |
|
|
in the Or1k architecture it is impossible
|
| 380 |
|
|
to nest interrupts. Interrupts must run to
|
| 381 |
|
|
completion before reenabling. If there is a
|
| 382 |
|
|
significant task to be done, then it should
|
| 383 |
|
|
run in a bottom half handler, similar to the
|
| 384 |
|
|
way Linux works. In theory though, even if
|
| 385 |
|
|
we do allow nested interrupts, there is no
|
| 386 |
|
|
reason for this flag, as it seems to be for
|
| 387 |
|
|
the purpose of restoring the normal stack in
|
| 388 |
|
|
place of the interrupt stack. We don't use a
|
| 389 |
|
|
separate exception stack, so this should not
|
| 390 |
|
|
be an issue for us. */
|
| 391 |
|
|
|
| 392 |
|
|
l.movhi r7,hi(__Thread_Dispatch_disable_level)
|
| 393 |
|
|
l.ori r7,r7,lo(__Thread_Dispatch_disable_level)
|
| 394 |
|
|
l.lwz r8,0(r7)
|
| 395 |
|
|
l.addi r8,r8,-1 # Decrement __Thread_Dispatch...
|
| 396 |
|
|
l.sw 0(r7),r8 # Memory stall likely here...
|
| 397 |
|
|
|
| 398 |
|
|
l.sfeqi r8,0 # Skip if _Thread_Dispatch != 0
|
| 399 |
|
|
l.bnf L4_2
|
| 400 |
|
|
l.movhi r7,hi(__Context_Switch_necessary)
|
| 401 |
|
|
|
| 402 |
|
|
l.ori r7,r7,lo(__Context_Switch_necessary)
|
| 403 |
|
|
l.lwz r8,0(r7)
|
| 404 |
|
|
|
| 405 |
|
|
l.movhi r7,hi(__ISR_Signals_to_thread_executing)
|
| 406 |
|
|
l.ori r7,r7,lo(__ISR_Signals_to_thread_executing)
|
| 407 |
|
|
l.lwz r12,0(r7)
|
| 408 |
|
|
|
| 409 |
|
|
l.sfeqi r8,0 # Skip if __Context... is false
|
| 410 |
|
|
l.bf L4_2
|
| 411 |
|
|
l.movhi r14,hi(__Thread_Dispatch)
|
| 412 |
|
|
|
| 413 |
|
|
l.sfeqi r12,0 # Skip if __ISR... is true
|
| 414 |
|
|
l.bnf L4_2
|
| 415 |
|
|
l.ori r14,r14,lo(__Thread_Dispatch)
|
| 416 |
|
|
|
| 417 |
|
|
l.jalr r14
|
| 418 |
|
|
l.sw 0(r7),r0 # Set __ISR... to false
|
| 419 |
|
|
|
| 420 |
|
|
L4_2:
|
| 421 |
|
|
l.lwz r9,0(r1) # Recover the return address
|
| 422 |
|
|
l.jr r9
|
| 423 |
|
|
l.addi r1,r1,8 # Reset the stack
|
| 424 |
|
|
|
| 425 |
|
|
.endproc ___user_function
|
| 426 |
|
|
.def ___user_function
|
| 427 |
|
|
.val .
|
| 428 |
|
|
.scl -1
|
| 429 |
|
|
.endef
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
/* Code wasted between here and 0x300 */
|
| 433 |
|
|
|
| 434 |
|
|
/**************************************/
|
| 435 |
|
|
/* Data Page Fault vector static code */
|
| 436 |
|
|
/**************************************/
|
| 437 |
|
|
.org 0x300
|
| 438 |
|
|
.proc ___data_page_fault
|
| 439 |
|
|
.global ___data_page_fault
|
| 440 |
|
|
___data_page_fault:
|
| 441 |
|
|
l.addi r1,r1,-80
|
| 442 |
|
|
l.sw 0(r1),r3
|
| 443 |
|
|
l.sw 28(r1),r11
|
| 444 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 445 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 446 |
|
|
l.lwz r11,12(r11)
|
| 447 |
|
|
l.j ___standard_exception
|
| 448 |
|
|
l.addi r3,r0,3
|
| 449 |
|
|
.endproc ___data_page_fault
|
| 450 |
|
|
|
| 451 |
|
|
/* Code wasted between here and 0x400 */
|
| 452 |
|
|
|
| 453 |
|
|
/*********************************************/
|
| 454 |
|
|
/* Instruction Page Fault vector static code */
|
| 455 |
|
|
/*********************************************/
|
| 456 |
|
|
.org 0x400
|
| 457 |
|
|
.proc ___insn_page_fault
|
| 458 |
|
|
.global ___insn_page_fault
|
| 459 |
|
|
___insn_page_fault:
|
| 460 |
|
|
l.addi r1,r1,-80
|
| 461 |
|
|
l.sw 0(r1),r3
|
| 462 |
|
|
l.sw 28(r1),r11
|
| 463 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 464 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 465 |
|
|
l.lwz r11,16(r11)
|
| 466 |
|
|
l.j ___standard_exception
|
| 467 |
|
|
l.addi r3,r0,4
|
| 468 |
|
|
.endproc ___insn_page_fault
|
| 469 |
|
|
|
| 470 |
|
|
/* Code wasted between here and 0x500 */
|
| 471 |
|
|
|
| 472 |
|
|
/**************************************/
|
| 473 |
|
|
/* Low Priority Interrupt static code */
|
| 474 |
|
|
/**************************************/
|
| 475 |
|
|
.org 0x500
|
| 476 |
|
|
.proc ___low_priority_int
|
| 477 |
|
|
.global ___low_priority_int
|
| 478 |
|
|
___low_priority_int:
|
| 479 |
|
|
l.addi r1,r1,-80
|
| 480 |
|
|
l.sw 0(r1),r3
|
| 481 |
|
|
l.sw 28(r1),r11
|
| 482 |
|
|
l.mfspr r3,r0,17 # Get the SR
|
| 483 |
|
|
l.addi r11,r0,-5 # r11 = 0xFFFFFFFB
|
| 484 |
|
|
l.and r11,r11,r3 # Clear the EIR bit
|
| 485 |
|
|
l.mtspr r0,r11,17 # Set the SR w/o INT
|
| 486 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 487 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 488 |
|
|
l.lwz r11,20(r11)
|
| 489 |
|
|
l.j ___standard_exception
|
| 490 |
|
|
l.addi r3,r0,5
|
| 491 |
|
|
.endproc ___low_priority_int
|
| 492 |
|
|
|
| 493 |
|
|
/* Code wasted between here and 0x600 */
|
| 494 |
|
|
|
| 495 |
|
|
/******************************************/
|
| 496 |
|
|
/* Alignment Exception vector static code */
|
| 497 |
|
|
/******************************************/
|
| 498 |
|
|
.org 0x600
|
| 499 |
|
|
.proc ___alignment_exception
|
| 500 |
|
|
.global ___alignment_exception
|
| 501 |
|
|
___alignment_exception:
|
| 502 |
|
|
l.addi r1,r1,-80
|
| 503 |
|
|
l.sw 0(r1),r3
|
| 504 |
|
|
l.sw 28(r1),r11
|
| 505 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 506 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 507 |
|
|
l.lwz r11,24(r11)
|
| 508 |
|
|
l.j ___standard_exception
|
| 509 |
|
|
l.addi r3,r0,6
|
| 510 |
|
|
.endproc ___alignment_exception
|
| 511 |
|
|
|
| 512 |
|
|
/* Code wasted between here and 0x700 */
|
| 513 |
|
|
|
| 514 |
|
|
/******************************************/
|
| 515 |
|
|
/* Illegal Instruction vector static code */
|
| 516 |
|
|
/******************************************/
|
| 517 |
|
|
.org 0x700
|
| 518 |
|
|
.proc ___illegal_instruction
|
| 519 |
|
|
.global ___illegal_instruction
|
| 520 |
|
|
___illegal_instruction:
|
| 521 |
|
|
l.addi r1,r1,-80
|
| 522 |
|
|
l.sw 0(r1),r3
|
| 523 |
|
|
l.sw 28(r1),r11
|
| 524 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 525 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 526 |
|
|
l.lwz r11,28(r11)
|
| 527 |
|
|
l.j ___standard_exception
|
| 528 |
|
|
l.addi r3,r0,7
|
| 529 |
|
|
.endproc ___illegal_instruction
|
| 530 |
|
|
|
| 531 |
|
|
/* Code wasted between here and 0x800 */
|
| 532 |
|
|
|
| 533 |
|
|
/***************************************/
|
| 534 |
|
|
/* High Priority Interrupt static code */
|
| 535 |
|
|
/***************************************/
|
| 536 |
|
|
.org 0x800
|
| 537 |
|
|
.proc ___high_priority_int
|
| 538 |
|
|
.global ___high_priority_int
|
| 539 |
|
|
___high_priority_int:
|
| 540 |
|
|
l.addi r1,r1,-80
|
| 541 |
|
|
l.sw 0(r1),r3
|
| 542 |
|
|
l.sw 28(r1),r11
|
| 543 |
|
|
l.mfspr r3,r0,17 # Get the SR
|
| 544 |
|
|
l.addi r11,r0,-5 # r11 = 0xFFFFFFFB
|
| 545 |
|
|
l.and r11,r11,r3 # Clear the EIR bit
|
| 546 |
|
|
l.mtspr r0,r11,17 # Set the SR w/o INT
|
| 547 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 548 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 549 |
|
|
l.lwz r11,32(r11)
|
| 550 |
|
|
l.j ___standard_exception
|
| 551 |
|
|
l.addi r3,r0,8
|
| 552 |
|
|
.endproc ___high_priority_int
|
| 553 |
|
|
|
| 554 |
|
|
/* Code wasted between here and 0x900 */
|
| 555 |
|
|
|
| 556 |
|
|
/********************************/
|
| 557 |
|
|
/* ITBL Miss vector static code */
|
| 558 |
|
|
/********************************/
|
| 559 |
|
|
.org 0x900
|
| 560 |
|
|
.proc ___ITBL_miss_exception
|
| 561 |
|
|
.global ___ITBL_miss_exception
|
| 562 |
|
|
___ITBL_miss_exception:
|
| 563 |
|
|
l.addi r1,r1,-80
|
| 564 |
|
|
l.sw 0(r1),r3
|
| 565 |
|
|
l.sw 28(r1),r11
|
| 566 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 567 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 568 |
|
|
l.lwz r11,36(r11)
|
| 569 |
|
|
l.j ___standard_exception
|
| 570 |
|
|
l.addi r3,r0,9
|
| 571 |
|
|
.endproc ___ITBL_miss_exception
|
| 572 |
|
|
|
| 573 |
|
|
/* Code wasted between here and 0xA00 */
|
| 574 |
|
|
|
| 575 |
|
|
/********************************/
|
| 576 |
|
|
/* DTBL Miss vector static code */
|
| 577 |
|
|
/********************************/
|
| 578 |
|
|
.org 0xA00
|
| 579 |
|
|
.proc ___DTBL_miss_exception
|
| 580 |
|
|
.global ___DTBL_miss_exception
|
| 581 |
|
|
___DTBL_miss_exception:
|
| 582 |
|
|
l.addi r1,r1,-80
|
| 583 |
|
|
l.sw 0(r1),r3
|
| 584 |
|
|
l.sw 28(r1),r11
|
| 585 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 586 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 587 |
|
|
l.lwz r11,40(r11)
|
| 588 |
|
|
l.j ___standard_exception
|
| 589 |
|
|
l.addi r3,r0,10
|
| 590 |
|
|
.endproc ___DTBL_miss_exception
|
| 591 |
|
|
|
| 592 |
|
|
/* Code wasted between here and 0xB00 */
|
| 593 |
|
|
|
| 594 |
|
|
/**************************************/
|
| 595 |
|
|
/* Range Exception vector static code */
|
| 596 |
|
|
/**************************************/
|
| 597 |
|
|
.org 0xB00
|
| 598 |
|
|
.proc ___range_exception
|
| 599 |
|
|
.global ___range_exception
|
| 600 |
|
|
___range_exception:
|
| 601 |
|
|
l.addi r1,r1,-80
|
| 602 |
|
|
l.sw 0(r1),r3
|
| 603 |
|
|
l.sw 28(r1),r11
|
| 604 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 605 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 606 |
|
|
l.lwz r11,44(r11)
|
| 607 |
|
|
l.j ___standard_exception
|
| 608 |
|
|
l.addi r3,r0,11
|
| 609 |
|
|
.endproc ___range_exception
|
| 610 |
|
|
|
| 611 |
|
|
/* Code wasted between here and 0xC00 */
|
| 612 |
|
|
|
| 613 |
|
|
/**********************************/
|
| 614 |
|
|
/* System Call vector static code */
|
| 615 |
|
|
/**********************************/
|
| 616 |
|
|
.org 0xC00
|
| 617 |
|
|
.proc ___system_call
|
| 618 |
|
|
.global ___system_call
|
| 619 |
|
|
___system_call:
|
| 620 |
|
|
l.addi r1,r1,-80
|
| 621 |
|
|
l.sw 0(r1),r3
|
| 622 |
|
|
l.sw 28(r1),r11
|
| 623 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 624 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 625 |
|
|
l.lwz r11,48(r11)
|
| 626 |
|
|
l.j ___standard_exception
|
| 627 |
|
|
l.addi r3,r0,12
|
| 628 |
|
|
.endproc ___system_call
|
| 629 |
|
|
|
| 630 |
|
|
/* Code wasted between here and 0xD00 */
|
| 631 |
|
|
|
| 632 |
|
|
/**********************************/
|
| 633 |
|
|
/* Breakpoint vector static code */
|
| 634 |
|
|
/**********************************/
|
| 635 |
|
|
.org 0xD00
|
| 636 |
|
|
.proc ___breakpoint
|
| 637 |
|
|
.global ___breakpoint
|
| 638 |
|
|
___breakpoint:
|
| 639 |
|
|
|
| 640 |
|
|
/* In keeping with the necessary requirements for
|
| 641 |
|
|
gdb to work, we are limiting this vector to
|
| 642 |
|
|
only 2 statements, which effect an immediate
|
| 643 |
|
|
return. At a later date, we may insert a debug
|
| 644 |
|
|
monitor here that will do even more, but for
|
| 645 |
|
|
now, this is all we want. */
|
| 646 |
|
|
l.rfe
|
| 647 |
|
|
l.nop
|
| 648 |
|
|
|
| 649 |
|
|
.endproc ___breakpoint
|
| 650 |
|
|
|
| 651 |
|
|
/* Code wasted between here and 0xE00 */
|
| 652 |
|
|
|
| 653 |
|
|
/*************************************/
|
| 654 |
|
|
/* Trap Exception vector static code */
|
| 655 |
|
|
/*************************************/
|
| 656 |
|
|
.org 0xE00
|
| 657 |
|
|
.proc ___trap_exception
|
| 658 |
|
|
.global ___trap_exception
|
| 659 |
|
|
___trap_exception:
|
| 660 |
|
|
l.addi r1,r1,-80
|
| 661 |
|
|
l.sw 0(r1),r3
|
| 662 |
|
|
l.sw 28(r1),r11
|
| 663 |
|
|
l.movhi r11,hi(_Or1k_Interrupt_Vectors)
|
| 664 |
|
|
l.ori r11,r11,lo(_Or1k_Interrupt_Vectors)
|
| 665 |
|
|
l.lwz r11,56(r11)
|
| 666 |
|
|
l.j ___standard_exception
|
| 667 |
|
|
l.addi r3,r0,14
|
| 668 |
|
|
.endproc ___trap_exception
|
| 669 |
|
|
|
| 670 |
|
|
/* Code wasted between here and 0x2000 */
|
| 671 |
|
|
|
| 672 |
|
|
/* Exceptions from 0xF00 to 0x1F00 are not defined */
|
| 673 |
|
|
/* in the Or1k architecture. They should be filled */
|
| 674 |
|
|
/* in here for other implementations. */
|
| 675 |
|
|
|
| 676 |
|
|
.org 0x2000 /* Start after exception vector table */
|
| 677 |
|
|
|
| 678 |
|
|
/*********************/
|
| 679 |
|
|
/* start */
|
| 680 |
|
|
/*********************/
|
| 681 |
|
|
|
| 682 |
|
|
/* This is where we jump to right after the reset exception
|
| 683 |
|
|
handler. The system configuration information should
|
| 684 |
|
|
be passed to us in a pointer in r4. Generally, the
|
| 685 |
|
|
reset vector will call this routine directly, and
|
| 686 |
|
|
the memory configuration information will be stored
|
| 687 |
|
|
in the ROM/Flash image. It was decided no attempt
|
| 688 |
|
|
would be made to automatically determine this
|
| 689 |
|
|
information by probing, as the scheme would be too
|
| 690 |
|
|
complex and inherently unreliable. */
|
| 691 |
|
|
|
| 692 |
|
|
/* Initialize strings and structures here */
|
| 693 |
|
|
L_program:
|
| 694 |
|
|
.ascii "RTEMS_or1k\000"
|
| 695 |
|
|
.align 4
|
| 696 |
|
|
L_argv:
|
| 697 |
|
|
.word L_program
|
| 698 |
|
|
|
| 699 |
|
|
.proc _start
|
| 700 |
|
|
.def _start
|
| 701 |
|
|
.val _start
|
| 702 |
|
|
.scl 2
|
| 703 |
|
|
.type 044
|
| 704 |
|
|
.endef
|
| 705 |
|
|
.global _start
|
| 706 |
|
|
_start:
|
| 707 |
|
|
|
| 708 |
|
|
/* Initialize the memory controller here!
|
| 709 |
|
|
Discussions with Rudi have stated that
|
| 710 |
|
|
the first few bytes of the ROM image should
|
| 711 |
|
|
contain a RAM map as opposed to trying to
|
| 712 |
|
|
figure out what to do based on probing. This
|
| 713 |
|
|
means a separate build of the OS for every
|
| 714 |
|
|
possible board configuration, but there
|
| 715 |
|
|
doesn't seem to be a better alternative. */
|
| 716 |
|
|
|
| 717 |
|
|
/*** FIX ME! Initialize the external memory controller! ***/
|
| 718 |
|
|
|
| 719 |
|
|
/* Move the data segment to RAM. Alternatively, we may
|
| 720 |
|
|
copy the text segment as well. For now, we'll assume
|
| 721 |
|
|
that the cache gives us sufficient performance that this
|
| 722 |
|
|
is not necessary. It will be very easy to add this later.
|
| 723 |
|
|
*/
|
| 724 |
|
|
l.movhi r4,hi(_etext)
|
| 725 |
|
|
l.ori r4,r4,lo(_etext)
|
| 726 |
|
|
l.movhi r5,hi(_BOTTOM_OF_MEMORY)
|
| 727 |
|
|
l.ori r5,r5,lo(_BOTTOM_OF_MEMORY)
|
| 728 |
|
|
l.lwz r5,0(r5) # Dereference it
|
| 729 |
|
|
/* l.add r5,r5,r4 # Place it in memory above the text segment*/
|
| 730 |
|
|
l.movhi r3,hi(_edata)
|
| 731 |
|
|
l.ori r3,r3,lo(_edata)
|
| 732 |
|
|
l.movhi r5,hi(_data_start)
|
| 733 |
|
|
l.ori r5,r5,lo(_data_start)
|
| 734 |
|
|
|
| 735 |
|
|
L3_0:
|
| 736 |
|
|
l.lwz r6,0(r4)
|
| 737 |
|
|
l.addi r5,r5,4
|
| 738 |
|
|
l.addi r4,r4,4
|
| 739 |
|
|
l.sfeq r3,r5
|
| 740 |
|
|
l.bnf L3_0
|
| 741 |
|
|
l.sw -4(r5),r6 # Minimize write after read stalls
|
| 742 |
|
|
|
| 743 |
|
|
/* Initialize the BSS segment */
|
| 744 |
|
|
l.movhi r3,hi(__end)
|
| 745 |
|
|
l.ori r3,r3,lo(__end)
|
| 746 |
|
|
/* l.sub r3,r3,r4
|
| 747 |
|
|
l.add r3,r3,r5*/
|
| 748 |
|
|
l.sfleu r3,r5
|
| 749 |
|
|
l.bf L3_2 # Check for no BSS segment!
|
| 750 |
|
|
l.nop
|
| 751 |
|
|
|
| 752 |
|
|
L3_1:
|
| 753 |
|
|
l.addi r5,r5,4
|
| 754 |
|
|
l.sfeq r5,r3
|
| 755 |
|
|
l.bnf L3_1
|
| 756 |
|
|
l.sw -4(r5),r0
|
| 757 |
|
|
|
| 758 |
|
|
L3_2:
|
| 759 |
|
|
/* Tell everyone where the heap begins */
|
| 760 |
|
|
l.movhi r4,hi(__mem_end)
|
| 761 |
|
|
l.ori r4,r4,lo(__mem_end)
|
| 762 |
|
|
l.sw 0(r4),r5
|
| 763 |
|
|
|
| 764 |
|
|
/* Due to what I consider a bug in RTEMS, the entire
|
| 765 |
|
|
heap must be zeroed. I think this is the dumbest thing
|
| 766 |
|
|
I've ever heard, but whatever turns them on. I'd rather
|
| 767 |
|
|
see the code which depends on this behavior fixed. I
|
| 768 |
|
|
myself have never written code which assumes zeroes
|
| 769 |
|
|
will be returned from memory allocated from the heap.
|
| 770 |
|
|
Anyway, if I don't do it here, I have to set a flag in
|
| 771 |
|
|
the CPU structure which then will do it anyway, but
|
| 772 |
|
|
from less efficient C code! Zero from here to the
|
| 773 |
|
|
stack pointer... One day when I'm old and gray maybe
|
| 774 |
|
|
I'll set this to random values instead and fix
|
| 775 |
|
|
whatever breaks. */
|
| 776 |
|
|
|
| 777 |
|
|
l.sw 0(r5),r0
|
| 778 |
|
|
l.sfeq r5,r1
|
| 779 |
|
|
l.bnf L3_3
|
| 780 |
|
|
l.addi r5,r5,4
|
| 781 |
|
|
|
| 782 |
|
|
L3_3:
|
| 783 |
|
|
l.addi r3,r0,1 /* Set argc to 1 */
|
| 784 |
|
|
l.movhi r4,hi(L_argv) /* Initialize argv */
|
| 785 |
|
|
l.ori r4,r4,lo(L_argv)
|
| 786 |
|
|
l.addi r5,r5,0 /* Set envp to NULL */
|
| 787 |
|
|
|
| 788 |
|
|
l.mfspr r11,r0,17 /* Get SR value */
|
| 789 |
|
|
l.ori r11,r11,0x4 /* Set interrupt enable bit */
|
| 790 |
|
|
l.jal _boot_card /* Boot up the card...run the OS */
|
| 791 |
|
|
l.mtspr r0,r11,17 /* Enable exceptions (DELAY) */
|
| 792 |
|
|
|
| 793 |
|
|
/* We're done. We exited normally. Shut down. */
|
| 794 |
|
|
l.jal __exit
|
| 795 |
|
|
l.nop
|
| 796 |
|
|
|
| 797 |
|
|
.endproc _start
|
| 798 |
|
|
.def _start
|
| 799 |
|
|
.val .
|
| 800 |
|
|
.scl -1
|
| 801 |
|
|
.endef
|
| 802 |
|
|
|
| 803 |
|
|
END_CODE
|
| 804 |
|
|
|
