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#
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# Quirks in the DY-4 DMV177
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#
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# $Id: QUIRKS,v 1.2 2001-09-27 12:00:30 chris Exp $
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#
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JTAG and Caching
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================
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If data or code caching is enabled on certain revisions of the PPC603e,
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then the JTAG emulator interface become disfunctional. You can not
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debug using the emulator on these chip revisions. On certain revisions,
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it is so bad that when code caching is enabled, you can not even
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download code reliably to the board.
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Caching and Peripherals
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=======================
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When caching is enabled, care must be exercised to insure that all
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peripheral addresses are still uncached.
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Exar 88681 Clock
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================
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This board uses a different clock for the Exar 88681 DUART than is
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documented in the Exar manual or the original MC68681 manual. This
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resulted in the need for the the mc68681 libchip driver to support
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BSP specific baud rate tables and the development of a DMV177
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specific baud rate table.
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In the end, this all works but you have a very limited range of
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useful baud rates on the 88681 ports compared to what would have
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been supported had DY-4 just followed the Exar or Motorola manual.
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SCC Addresses
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=============
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The full set of SCC addresses is not documented in the DY-4 manual
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and they are not ordered as one would expect. Normally the four
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SCC registers are ordered Control A, Data A, Control B, and Data B.
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DY-4 orders them with B first.
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This required extra time to debug.
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SCV64 and the Foundation Firmware
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=================================
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DY-4 technical support did not offer code to determine which interrupt
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sources were pending at the SCV64. They recommended calling into the
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Foundation Firmware ROM monitor to figure this out. The Foundation
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Firmware did not recognize enough interrupts on this board to be useful.
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In the end, we gave up on their technical support's recommendation
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and directly manipulated the SVC64. This is what we wanted to do in
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the first place but we got no information from them to aid in this.
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Luckily, the manual does document enough of DY-4's mapping of the specific
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interrupt sources to make this work.
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Z85C30 SCC Clock Speed
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======================
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The Z85C30 SCC can be factory configured for 10 Mhz or 2.4616 Mhz. Code
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had to be added to dynamically determine which clock was installed.
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The board we had used a 10 Mhz clock. No testing was done with a 2.4616 Mhz
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clock.
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P2 Octopus Cable
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================
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DY-4's P2 breakout is large and a bit unwieldy. It was difficult to
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fight into the VME cage we used. The SCSI connector comes off the
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side and is very stiff thus making it difficult to route around
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anything in the back of the cage. We gave up on trying to use
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it in the first few slots of OAR's cage.
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