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unneback |
/* flashentry.s
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*
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* This file contains the entry code for RTEMS programs starting
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* directly from Flash.
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*
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* Author: Thomas Doerfler
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* IMD Ingenieurbuero fuer Microcomputertechnik
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*
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* COPYRIGHT (c) 1998 by IMD
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*
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* Changes from IMD are covered by the original distributions terms.
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* This file has been derived from the papyrus BSP:
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*
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* This file contains the entry veneer for RTEMS programs
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* stored in Papyrus' flash ROM.
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*
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* Author: Andrew Bray
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*
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of i-cubed limited not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* i-cubed limited makes no representations about the suitability
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* of this software for any purpose.
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*
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* $Id: flashentry.S,v 1.2 2001-09-27 12:00:36 chris Exp $
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*/
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#include "asm.h"
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#include
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/*----------------------------------------------------------------------------
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* Reset_entry.
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*---------------------------------------------------------------------------*/
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#if PPC_ASM == PPC_ASM_ELF
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.section .reset,"ax",@progbits
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/* this section MUST be located at absolute address 0xFFFFFFFC
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or last word of EPROM */
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#else
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.csect .text[PR]
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#endif
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ba flash_entry /* this is the first instruction after reset */
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.previous
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/*----------------------------------------------------------------------------
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* ROM Vector area.
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*---------------------------------------------------------------------------*/
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#if PPC_ASM == PPC_ASM_ELF
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.section .entry,"ax",@progbits
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#else
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.csect .text[PR]
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#endif
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PUBLIC_VAR (flash_entry)
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SYM (flash_entry):
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bl .startup /* call startup, link reg points to base_addr */
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base_addr:
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/*----------------------------------------------------------------------------
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* Parameters from linker
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*---------------------------------------------------------------------------*/
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toc_pointer:
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#if PPC_ASM == PPC_ASM_ELF
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.long s.got
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#else
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.long TOC[tc0]
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#endif
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text_length:
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.long text.size
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text_addr:
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.long text.start
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copy_src:
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.long copy.src
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copy_length:
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.long copy.size
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copy_dest:
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.long copy.dest
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bss_length:
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.long bss.size
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bss_addr:
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.long bss.start
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stack_top:
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.long stack.end
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/*----------------------------------------------------------------------------
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* from Reset_entry.
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*---------------------------------------------------------------------------*/
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.startup:
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/* Get start address, r1 points to label base_addr */
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mflr r1
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/* Set up Bank regs, cache etc. */
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/* set up bank register BR0 for Flash-EPROM:
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* NOTE: bank size should stay 1MByte, this is standard size
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* after RESET
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* base addr = Fffxxxxx -> 0b11111111........................
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* bank size = 1 MByte -> 0b........000..................... (std)
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* bank use = readonly -> 0b...........01...................
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* seq. fill = targ frst-> 0b.............0..................
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* burst mode= enable -> 0b..............1.................
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* bus width = 8 bit -> 0b...............00...............
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* ready pin = disable -> 0b.................0..............
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* first wait= 2 clocks -> 0b..................0010..........
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* burst wait= 2 clocks -> 0b......................10........
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* CSon time = 0 clocks -> 0b........................0.......
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* OEon time = 0 clocks -> 0b.........................0......
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* WBon time = 1 clocks -> 0b..........................1.....
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* WBoff time= 0 clocks -> 0b...........................0....
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* Hold time = 1 clocks -> 0b............................001.
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* ram type = SRAM(ign)-> 0b...............................1
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* value 0b11111111000010100000101000100011
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* 0x F F 0 A 0 A 2 3
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*/
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lis r2,0xFF0A
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ori r2,r2,0x0A23
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mtdcr br0,r2 /* write to DCR BR0 */
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/*--------------------------------------------------------------------
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* test various RAM configurations (from big to small per bank)
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*------------------------------------------------------------------*/
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/*--------------------------------------------------------------------
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* test RAM config 16 MByte (1x4Mx32Bit)
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*------------------------------------------------------------------*/
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/* set up bank register BR7 for DRAM:
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* base addr = 000xxxxx -> 0b00000000........................
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* bank size = 16MByte -> 0b........100.....................
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* bank use = readwrite-> 0b...........11...................
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* seq. fill = targ.frst-> 0b.............0..................
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* early RAS = disabled -> 0b..............0.................
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| 138 |
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* bus width = 32bit -> 0b...............10...............
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* adr mux = internal -> 0b.................0..............
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* RAS to CAS= 2 clocks -> 0b..................1.............
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| 141 |
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* Alt. Rfrsh= normal -> 0b...................0............
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* page mode = enabled -> 0b....................1...........
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* first wait= 1 clocks -> 0b.....................01.........
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* burst wait= 1 clocks -> 0b.......................01.......
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* precharge = 1 clocks -> 0b.........................0......
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* RAS Rfrsh = 2 clocks -> 0b..........................1.....
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* Rfrsh Itvl= 512 clks -> 0b...........................1000.
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* ram type = DRAM -> 0b...............................0
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* value 0b00000000100110010010101010110000
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* 0x 0 0 9 9 2 A B 0
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*/
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lis r2,0x0099
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ori r2,r2,0x2AB0
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mtdcr br7,r2 /* write to DCR BR7*/
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lis r2,0x0000 /* start address = 0x00000000 */
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lis r3,0x0100 /* size 16 MB = 0x01000000 */
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bl ramacc /* test memory accessibility */
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cmpi 0,0,r4,0 /* memory ok? else test smaller size */
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bne ramcfgt18
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/*--------------------------------------------------------------------
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* test RAM config 32 MByte (2x4Mx32Bit)
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*------------------------------------------------------------------*/
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/* set up bank register BR7 like above
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* set up bank register BR6 for DRAM:
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* base addr = 010xxxxx -> 0b00010000........................
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* bank size = 16MByte -> 0b........100..................... (for now)
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| 169 |
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* bank use = readwrite-> 0b...........11...................
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| 170 |
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* seq. fill = targ.frst-> 0b.............0..................
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| 171 |
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* early RAS = disabled -> 0b..............0.................
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| 172 |
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* bus width = 32bit -> 0b...............10...............
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| 173 |
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* adr mux = internal -> 0b.................0..............
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| 174 |
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* RAS to CAS= 2 clocks -> 0b..................1.............
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* Alt. Rfrsh= normal -> 0b...................0............
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| 176 |
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* page mode = enabled -> 0b....................1...........
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| 177 |
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* first wait= 1 clocks -> 0b.....................01.........
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* burst wait= 1 clocks -> 0b.......................01.......
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* precharge = 1 clocks -> 0b.........................0......
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* RAS Rfrsh = 2 clocks -> 0b..........................1.....
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* Rfrsh Itvl= 512 clks -> 0b...........................1000.
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* ram type = DRAM -> 0b...............................0
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* value 0b00010000100110010010101010110000
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* 0x 1 0 9 9 2 A B 0
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*/
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lis r2,0x1099
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ori r2,r2,0x2AB0
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mtdcr br6,r2 /* write to DCR BR6*/
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| 190 |
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lis r2,0x0100 /* start address = 0x01000000 */
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lis r3,0x0100 /* size 16 MB = 0x01000000 */
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bl ramacc /* test memory accessibility */
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| 193 |
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cmpi 0,0,r4,0 /* memory ok? else test smaller size */
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| 194 |
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beq ramcfgok /* ok, we found configuration... +/
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| 195 |
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| 196 |
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lis r2,0x0000 /* disable BR6, config not ok */
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| 197 |
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mtdcr br6,r2 /* write to DCR BR6*/
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| 198 |
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b ramcfgok /* and finish configuration */
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| 199 |
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|
| 200 |
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ramcfgt18:
|
| 201 |
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/*--------------------------------------------------------------------
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| 202 |
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* test RAM config 8 MByte (1x2Mx32Bit)
|
| 203 |
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*------------------------------------------------------------------*/
|
| 204 |
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/* set up bank register BR7 for DRAM:
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| 205 |
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* base addr = 000xxxxx -> 0b00000000........................
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| 206 |
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* bank size = 8MByte -> 0b........011.....................
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| 207 |
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* bank use = readwrite-> 0b...........11...................
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| 208 |
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* seq. fill = targ.frst-> 0b.............0..................
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| 209 |
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* early RAS = disabled -> 0b..............0.................
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| 210 |
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* bus width = 32bit -> 0b...............10...............
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| 211 |
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* adr mux = internal -> 0b.................0..............
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| 212 |
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* RAS to CAS= 2 clocks -> 0b..................1.............
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| 213 |
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* Alt. Rfrsh= normal -> 0b...................0............
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| 214 |
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* page mode = enabled -> 0b....................1...........
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| 215 |
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* first wait= 1 clocks -> 0b.....................01.........
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| 216 |
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* burst wait= 1 clocks -> 0b.......................01.......
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| 217 |
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* precharge = 1 clocks -> 0b.........................0......
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| 218 |
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* RAS Rfrsh = 2 clocks -> 0b..........................1.....
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| 219 |
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* Rfrsh Itvl= 512 clks -> 0b...........................1000.
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| 220 |
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* ram type = DRAM -> 0b...............................0
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| 221 |
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* value 0b00000000011110010010101010110000
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| 222 |
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* 0x 0 0 7 9 2 A B 0
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| 223 |
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*/
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| 224 |
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lis r2,0x0079
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| 225 |
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ori r2,r2,0x2AB0
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| 226 |
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mtdcr br7,r2 /* write to DCR BR7 */
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| 227 |
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| 228 |
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lis r2,0x0000 /* start address = 0x00000000 */
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| 229 |
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lis r3,0x0080 /* size 8 MB = 0x00800000 */
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| 230 |
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bl ramacc /* test memory accessibility */
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| 231 |
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cmpi 0,0,r4,0 /* memory ok? else test smaller size */
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| 232 |
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bne ramcfgt14
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| 233 |
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|
| 234 |
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/*--------------------------------------------------------------------
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| 235 |
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* test RAM config 16 MByte (2x2Mx32Bit)
|
| 236 |
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*------------------------------------------------------------------*/
|
| 237 |
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/* set up bank register BR7 like above
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| 238 |
|
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* set up bank register BR6 for DRAM:
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| 239 |
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* base addr = 008xxxxx -> 0b00001000........................
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| 240 |
|
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* bank size = 08MByte -> 0b........011..................... (for now)
|
| 241 |
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* bank use = readwrite-> 0b...........11...................
|
| 242 |
|
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* seq. fill = targ.frst-> 0b.............0..................
|
| 243 |
|
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* early RAS = disabled -> 0b..............0.................
|
| 244 |
|
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* bus width = 32bit -> 0b...............10...............
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| 245 |
|
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* adr mux = internal -> 0b.................0..............
|
| 246 |
|
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* RAS to CAS= 2 clocks -> 0b..................1.............
|
| 247 |
|
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* Alt. Rfrsh= normal -> 0b...................0............
|
| 248 |
|
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* page mode = enabled -> 0b....................1...........
|
| 249 |
|
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* first wait= 1 clocks -> 0b.....................01.........
|
| 250 |
|
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* burst wait= 1 clocks -> 0b.......................01.......
|
| 251 |
|
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* precharge = 1 clocks -> 0b.........................0......
|
| 252 |
|
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* RAS Rfrsh = 2 clocks -> 0b..........................1.....
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| 253 |
|
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* Rfrsh Itvl= 512 clks -> 0b...........................1000.
|
| 254 |
|
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* ram type = DRAM -> 0b...............................0
|
| 255 |
|
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* value 0b00001000011110010010101010110000
|
| 256 |
|
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* 0x 0 8 7 9 2 A B 0
|
| 257 |
|
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*/
|
| 258 |
|
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lis r2,0x0879
|
| 259 |
|
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ori r2,r2,0x2AB0
|
| 260 |
|
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mtdcr br6,r2 /* write to DCR BR6*/
|
| 261 |
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|
| 262 |
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lis r2,0x0080 /* start address = 0x00800000 */
|
| 263 |
|
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lis r3,0x0080 /* size 8 MB = 0x00800000 */
|
| 264 |
|
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bl ramacc /* test memory accessibility */
|
| 265 |
|
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cmpi 0,0,r4,0 /* memory ok? else test smaller size */
|
| 266 |
|
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beq ramcfgok /* ok, we found configuration... +/
|
| 267 |
|
|
|
| 268 |
|
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lis r2,0x0000 /* disable BR6, config not ok */
|
| 269 |
|
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mtdcr br6,r2 /* write to DCR BR6*/
|
| 270 |
|
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b ramcfgok /* and finish configuration */
|
| 271 |
|
|
|
| 272 |
|
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ramcfgt14:
|
| 273 |
|
|
/*--------------------------------------------------------------------
|
| 274 |
|
|
* test RAM config 4 MByte (1x1Mx32Bit)
|
| 275 |
|
|
*------------------------------------------------------------------*/
|
| 276 |
|
|
/* set up bank register BR7 for DRAM:
|
| 277 |
|
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* base addr = 000xxxxx -> 0b00000000........................
|
| 278 |
|
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* bank size = 4MByte -> 0b........010.....................
|
| 279 |
|
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* bank use = readwrite-> 0b...........11...................
|
| 280 |
|
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* seq. fill = targ.frst-> 0b.............0..................
|
| 281 |
|
|
* early RAS = disabled -> 0b..............0.................
|
| 282 |
|
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* bus width = 32bit -> 0b...............10...............
|
| 283 |
|
|
* adr mux = internal -> 0b.................0..............
|
| 284 |
|
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* RAS to CAS= 2 clocks -> 0b..................1.............
|
| 285 |
|
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* Alt. Rfrsh= normal -> 0b...................0............
|
| 286 |
|
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* page mode = enabled -> 0b....................1...........
|
| 287 |
|
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* first wait= 1 clocks -> 0b.....................01.........
|
| 288 |
|
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* burst wait= 1 clocks -> 0b.......................01.......
|
| 289 |
|
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* precharge = 1 clocks -> 0b.........................0......
|
| 290 |
|
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* RAS Rfrsh = 2 clocks -> 0b..........................1.....
|
| 291 |
|
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* Rfrsh Itvl= 512 clks -> 0b...........................1000.
|
| 292 |
|
|
* ram type = DRAM -> 0b...............................0
|
| 293 |
|
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* value 0b00000000010110010010101010110000
|
| 294 |
|
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* 0x 0 0 5 9 2 A B 0
|
| 295 |
|
|
*/
|
| 296 |
|
|
/*
|
| 297 |
|
|
* FIXME: this is the minimum size supported, should test and
|
| 298 |
|
|
* report error, when failed
|
| 299 |
|
|
*/
|
| 300 |
|
|
lis r2,0x0059
|
| 301 |
|
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ori r2,r2,0x2AB0
|
| 302 |
|
|
mtdcr br7,r2 /* write to DCR BR7*/
|
| 303 |
|
|
|
| 304 |
|
|
/*--------------------------------------------------------------------
|
| 305 |
|
|
* test RAM config 8 MByte (2x1Mx32Bit)
|
| 306 |
|
|
*------------------------------------------------------------------*/
|
| 307 |
|
|
/* set up bank register BR7 like above
|
| 308 |
|
|
* set up bank register BR6 for DRAM:
|
| 309 |
|
|
* base addr = 004xxxxx -> 0b00000100........................
|
| 310 |
|
|
* bank size = 4MByte -> 0b........010..................... (for now)
|
| 311 |
|
|
* bank use = readwrite-> 0b...........11...................
|
| 312 |
|
|
* seq. fill = targ.frst-> 0b.............0..................
|
| 313 |
|
|
* early RAS = disabled -> 0b..............0.................
|
| 314 |
|
|
* bus width = 32bit -> 0b...............10...............
|
| 315 |
|
|
* adr mux = internal -> 0b.................0..............
|
| 316 |
|
|
* RAS to CAS= 2 clocks -> 0b..................1.............
|
| 317 |
|
|
* Alt. Rfrsh= normal -> 0b...................0............
|
| 318 |
|
|
* page mode = enabled -> 0b....................1...........
|
| 319 |
|
|
* first wait= 1 clocks -> 0b.....................01.........
|
| 320 |
|
|
* burst wait= 1 clocks -> 0b.......................01.......
|
| 321 |
|
|
* precharge = 1 clocks -> 0b.........................0......
|
| 322 |
|
|
* RAS Rfrsh = 2 clocks -> 0b..........................1.....
|
| 323 |
|
|
* Rfrsh Itvl= 512 clks -> 0b...........................1000.
|
| 324 |
|
|
* ram type = DRAM -> 0b...............................0
|
| 325 |
|
|
* value 0b00000100010110010010101010110000
|
| 326 |
|
|
* 0x 0 4 5 9 2 A B 0
|
| 327 |
|
|
*/
|
| 328 |
|
|
lis r2,0x0459
|
| 329 |
|
|
ori r2,r2,0x2AB0
|
| 330 |
|
|
mtdcr br6,r2 /* write to DCR BR6*/
|
| 331 |
|
|
|
| 332 |
|
|
lis r2,0x0040 /* start address = 0x00400000 */
|
| 333 |
|
|
lis r3,0x0040 /* size 4 MB = 0x00400000 */
|
| 334 |
|
|
bl ramacc /* test memory accessibility */
|
| 335 |
|
|
cmpi 0,0,r4,0 /* memory ok? else test smaller size */
|
| 336 |
|
|
beq ramcfgok /* ok, we found configuration... +/
|
| 337 |
|
|
|
| 338 |
|
|
lis r2,0x0000 /* disable BR6, config not ok */
|
| 339 |
|
|
mtdcr br6,r2 /* write to DCR BR6*/
|
| 340 |
|
|
b ramcfgok /* and finish configuration */
|
| 341 |
|
|
|
| 342 |
|
|
ramcfgok:
|
| 343 |
|
|
/*--------------------------------------------------------------------
|
| 344 |
|
|
* init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK
|
| 345 |
|
|
* we will return here.
|
| 346 |
|
|
*-------------------------------------------------------------------*/
|
| 347 |
|
|
bl rom2ram
|
| 348 |
|
|
|
| 349 |
|
|
/* clear caches */
|
| 350 |
|
|
addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT
|
| 351 |
|
|
mtctr r2 /* count the loops needed... */
|
| 352 |
|
|
xor r2,r2,r2 /* start at adr zero */
|
| 353 |
|
|
icinvlp:
|
| 354 |
|
|
iccci 0,r2
|
| 355 |
|
|
addi r2,r2,PPC_CACHE_ALIGNMENT
|
| 356 |
|
|
bdnz icinvlp
|
| 357 |
|
|
|
| 358 |
|
|
addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT
|
| 359 |
|
|
mtctr r2 /* count the loops needed... */
|
| 360 |
|
|
xor r2,r2,r2 /* start at adr 0 */
|
| 361 |
|
|
dcinvlp:
|
| 362 |
|
|
dccci 0,r2
|
| 363 |
|
|
addi r2,r2,PPC_CACHE_ALIGNMENT
|
| 364 |
|
|
bdnz dcinvlp
|
| 365 |
|
|
/*--------------------------------------------------------------------
|
| 366 |
|
|
* Enable two 128MB cachable regions.
|
| 367 |
|
|
* FEPROM is cachable at 0xFFF00000..0xFFFFFFFF
|
| 368 |
|
|
* DRAM is cachable at 0x00000000..0x00FFFFFF
|
| 369 |
|
|
* FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF
|
| 370 |
|
|
* DRAM is noncachable at 0x80000000..0x80FFFFFF
|
| 371 |
|
|
*-------------------------------------------------------------------*/
|
| 372 |
|
|
addis r2,r0,0x8000
|
| 373 |
|
|
addi r2,r2,0x0001
|
| 374 |
|
|
|
| 375 |
|
|
mtspr iccr, r2 /* ICCR */
|
| 376 |
|
|
mtspr dccr, r2 /* DCCR */
|
| 377 |
|
|
|
| 378 |
|
|
.extern SYM(__vectors)
|
| 379 |
|
|
|
| 380 |
|
|
lis r2,__vectors@h /* set EVPR exc. vector prefix */
|
| 381 |
|
|
mtspr evpr,r2
|
| 382 |
|
|
|
| 383 |
|
|
lis r2,0x0000
|
| 384 |
|
|
ori r2,r2,0x0000
|
| 385 |
|
|
mtmsr r2 /* set default msr */
|
| 386 |
|
|
lis r2,0x0000 /* do not allow critical IRQ */
|
| 387 |
|
|
ori r2,r2,0x0000
|
| 388 |
|
|
mtdcr exier, r2 /* disable all external IRQs */
|
| 389 |
|
|
|
| 390 |
|
|
addi r2,r0,-1 /* r2 = 0xffffffff */
|
| 391 |
|
|
mtdcr exisr, r2 /* clear all pendingdisable IRQs */
|
| 392 |
|
|
|
| 393 |
|
|
/*--------------------------------------------------------------------
|
| 394 |
|
|
* C_setup.
|
| 395 |
|
|
*-------------------------------------------------------------------*/
|
| 396 |
|
|
|
| 397 |
|
|
lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
|
| 398 |
|
|
lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
|
| 399 |
|
|
|
| 400 |
|
|
addi r1,r1,-56 /* start stack at data_addr - 56 */
|
| 401 |
|
|
addi r3,r0,0x0 /* clear r3 */
|
| 402 |
|
|
stw r3, 0(r1) /* Clear stack chain */
|
| 403 |
|
|
stw r3, 4(r1)
|
| 404 |
|
|
stw r3, 8(r1)
|
| 405 |
|
|
stw r3, 12(r1)
|
| 406 |
|
|
.extern SYM (boot_card)
|
| 407 |
|
|
b SYM (boot_card) /* call the first C routine */
|
| 408 |
|
|
|
| 409 |
|
|
/*----------------------------------------------------------------------------
|
| 410 |
|
|
* Rom2ram.
|
| 411 |
|
|
*---------------------------------------------------------------------------*/
|
| 412 |
|
|
rom2ram:
|
| 413 |
|
|
lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */
|
| 414 |
|
|
lwz r3,copy_length-base_addr(r1) /* data length */
|
| 415 |
|
|
rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */
|
| 416 |
|
|
mtctr r3 /* set ctr reg */
|
| 417 |
|
|
/*--------------------------------------------------------------------
|
| 418 |
|
|
* Calculate offset of data in image.
|
| 419 |
|
|
*-------------------------------------------------------------------*/
|
| 420 |
|
|
lwz r4,copy_src-base_addr(r1) /* get start of copy area */
|
| 421 |
|
|
move_data:
|
| 422 |
|
|
lswi r6,r4,0x4 /* load r6 */
|
| 423 |
|
|
stswi r6,r2,0x4 /* store r6 */
|
| 424 |
|
|
addi r4,r4,0x4 /* update r4 */
|
| 425 |
|
|
addi r2,r2,0x4 /* update r2 */
|
| 426 |
|
|
bdnz move_data /* decrement counter and loop */
|
| 427 |
|
|
/*--------------------------------------------------------------------
|
| 428 |
|
|
* Data move finished, zero out bss.
|
| 429 |
|
|
*-------------------------------------------------------------------*/
|
| 430 |
|
|
lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
|
| 431 |
|
|
lwz r3,bss_length-base_addr(r1) /* bss length */
|
| 432 |
|
|
rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */
|
| 433 |
|
|
beqlr /* no bss */
|
| 434 |
|
|
mtctr r3 /* set ctr reg */
|
| 435 |
|
|
xor r6,r6,r6 /* r6 = 0 */
|
| 436 |
|
|
clear_bss:
|
| 437 |
|
|
stswi r6,r2,0x4 /* store r6 */
|
| 438 |
|
|
addi r2,r2,0x4 /* update r2 */
|
| 439 |
|
|
bdnz clear_bss /* decrement counter and loop */
|
| 440 |
|
|
blr /* return */
|
| 441 |
|
|
|
| 442 |
|
|
/*----------------------------------------------------------------------------
|
| 443 |
|
|
* ramacc test accessibility of RAM
|
| 444 |
|
|
* input: r2 = start address, r3 = length (in byte)
|
| 445 |
|
|
* output: r4 = 0 -> ok, !=0 -> fail
|
| 446 |
|
|
*---------------------------------------------------------------------------*/
|
| 447 |
|
|
ramacc:
|
| 448 |
|
|
xor r4,r4,r4 /* r4 = 0 */
|
| 449 |
|
|
stw r4,0(r2) /* init ram at start address */
|
| 450 |
|
|
addi r4,r0,0x04 /* set start shift */
|
| 451 |
|
|
ramaccf1:
|
| 452 |
|
|
cmp 0,0,r4,r3 /* compare with length */
|
| 453 |
|
|
bge ramaccfx /* r4 >= r3? then finished */
|
| 454 |
|
|
add r5,r4,r2 /* get next address to fill */
|
| 455 |
|
|
stw r4,0(r5) /* store new pattern */
|
| 456 |
|
|
add r4,r4,r4 /* r4 = r4*2 */
|
| 457 |
|
|
b ramaccf1 /* and then next loop */
|
| 458 |
|
|
|
| 459 |
|
|
ramaccfx:
|
| 460 |
|
|
lwz r4,0(r2) /* get memory at start adr */
|
| 461 |
|
|
blr
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
#if PPC_ABI == PPC_ABI_POWEROPEN
|
| 465 |
|
|
DESCRIPTOR (startup)
|
| 466 |
|
|
#endif
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
|
