OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [helas403/] [startup/] [linkcmds.dl] - Blame information for rev 593

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  This file contains directives for the GNU linker which are specific
3
 *  to the helas403
4
 *  This file is intended to be used together with dlentry.s
5
 *  it will generate downloadable code
6
 *
7
 *  $Id: linkcmds.dl,v 1.2 2001-09-27 12:00:36 chris Exp $
8
 */
9
 
10
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
11
              "elf32-powerpc")
12
OUTPUT_ARCH(powerpc)
13
 SEARCH_DIR(/usr/local/powerpc-rtems/lib);
14
 
15
ENTRY(download_entry)
16
 
17
MEMORY
18
  {
19
        RAM : ORIGIN = 0, LENGTH = 8M
20
        FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
21
  }
22
 
23
SECTIONS
24
{
25
  .vectors : 0x00010100
26
  {
27
    *(.vectors)
28
  } > RAM
29
 
30
  .text :
31
  {
32
     text.start = . ;
33
     *(.entry)
34
     *(.entry2)
35
     *(.text)
36
     *(.rodata)
37
     *(.rodata1)
38
     *(.descriptors)
39
     *(rom_ver)
40
     etext = ALIGN(0x10);
41
     _etext = .;
42
 
43
 
44
     __CTOR_LIST__ = .;
45
     LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
46
     *(.ctors)
47
     LONG(0)
48
     __CTOR_END__ = .;
49
 
50
     __DTOR_LIST__ = .;
51
     LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
52
     *(.dtors)
53
     LONG(0)
54
     __DTOR_END__ = .;
55
 
56
     *(.lit)
57
     *(.shdata)
58
     *(.init)
59
     *(.fini)
60
     _endtext = ALIGN(0x10);
61
     text.end = .;
62
  } > RAM
63
 
64
  text.size = text.end - text.start;
65
 
66
  /* R/W Data */
67
  .data :
68
  {
69
    *(.data)
70
    *(.data1)
71
    PROVIDE (__SDATA_START__ = .);
72
    *(.sdata)
73
  } > RAM
74
 
75
  PROVIDE (__EXCEPT_START__ = .);
76
  .gcc_except_table   :
77
  {
78
        *(.gcc_except_table)
79
  } >RAM
80
  PROVIDE (__EXCEPT_END__ = .);
81
 
82
  __GOT_START__ = .;
83
  .got :
84
  {
85
     s.got = .;
86
     *(.got.plt) *(.got)
87
  } > RAM
88
  __GOT_END__ = .;
89
 
90
  .got1 :
91
  {
92
        *(.got1)
93
  } >RAM
94
 
95
  PROVIDE (__GOT2_START__ = .);
96
  PROVIDE (_GOT2_START_ = .);
97
  .got2           :
98
  {
99
        *(.got2)
100
  } >RAM
101
  PROVIDE (__GOT2_END__ = .);
102
  PROVIDE (_GOT2_END_ = .);
103
 
104
  PROVIDE (__FIXUP_START__ = .);
105
  PROVIDE (_FIXUP_START_ = .);
106
  .fixup          : { *(.fixup)         } >RAM
107
  PROVIDE (_FIXUP_END_ = .);
108
  PROVIDE (__FIXUP_END__ = .);
109
 
110
  PROVIDE (__SDATA2_START__ = .);
111
  .sdata2         : { *(.sdata2)        } >RAM
112
  .sbss2          : { *(.sbss2)         } >RAM
113
  PROVIDE (__SBSS2_END__ = .);
114
 
115
  .sbss2          : { *(.sbss2)         } >RAM
116
  PROVIDE (__SBSS2_END__ = .);
117
 
118
  __SBSS_START__ = .;
119
  .bss :
120
  {
121
    bss.start = .;
122
    *(.bss) *(.sbss) *(COMMON)
123
    bss.end = ALIGN(4);
124
  } > RAM
125
  __SBSS_END__ = .;
126
 
127
  bss.size = bss.end - bss.start;
128
  PROVIDE(_end = bss.end);
129
 
130
  .line 0 : { *(.line) }
131
  .debug 0 : { *(.debug) }
132
  .debug_sfnames 0 : { *(.debug_sfnames) }
133
  .debug_srcinfo 0 : { *(.debug_srcinfo) }
134
  .debug_pubnames 0 : { *(.debug_pubnames) }
135
  .debug_aranges 0 : { *(.debug_aranges) }
136
  .debug_aregion 0 : { *(.debug_aregion) }
137
  .debug_macinfo 0 : { *(.debug_macinfo) }
138
  .stab 0 : { *(.stab) }
139
  .stabstr 0 : { *(.stabstr) }
140
}
141
 
142
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.