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unneback |
/*
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* This file contains the TTY driver table for the PPCn_60x
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*
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* COPYRIGHT (c) 1998 by Radstone Technology
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*
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*
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* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
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* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
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* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
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*
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* You are hereby granted permission to use, copy, modify, and distribute
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* this file, provided that this notice, plus the above copyright notice
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* and disclaimer, appears in all copies. Radstone Technology will provide
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* no support for this code.
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*
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* $Id: config.c,v 1.2 2001-09-27 12:00:49 chris Exp $
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*/
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#include <libchip/serial.h>
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#include <libchip/mc68681.h>
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#include <libchip/z85c30.h>
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#include "i8042vga.h"
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#include "ns16550cfg.h"
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#include "z85c30cfg.h"
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#include <pci.h>
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#define PMX1553_BUS 2
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#define PMX1553_SLOT 1
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/*
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* Based on BSP configuration information decide whether to do polling IO
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* or interrupt driven IO.
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*/
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#if (CONSOLE_USE_INTERRUPTS)
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#define NS16550_FUNCTIONS &ns16550_fns
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#define Z85C30_FUNCTIONS &z85c30_fns
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#else
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#define NS16550_FUNCTIONS &ns16550_fns_polled
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#define Z85C30_FUNCTIONS &z85c30_fns_polled
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#endif
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/*
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* Configuration specific probe routines
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*/
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static boolean config_PMX1553_probe(int minor);
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static boolean config_z85c30_probe(int minor);
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/*
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* The following table configures the console drivers used in this BSP.
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*
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* The first entry which, when probed, is available, will be named /dev/console,
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* all others being given the name indicated.
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*
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* Each field is interpreted thus:
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*
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* sDeviceName This is the name of the device.
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* pDeviceFns This is a pointer to the set of driver routines to use.
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* pDeviceFlow This is a pointer to the set of flow control routines to
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* use. Serial device drivers will typically supply RTSCTS
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* and DTRCTS handshake routines for DCE to DCE communication,
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* however for DCE to DTE communication, no such routines
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* should be necessary as RTS will be driven automatically
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* when the transmitter is active.
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* ulMargin The high water mark in the input buffer is set to the buffer
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* size less ulMargin. Once this level is reached, the driver's
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* flow control routine used to stop the remote transmitter will
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* be called. This figure should be greater than or equal to
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* the number of stages of FIFO between the transmitter and
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* receiver.
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* ulHysteresis After the high water mark specified by ulMargin has been
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* reached, the driver's routine to re-start the remote
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* transmitter will be called once the level in the input
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* buffer has fallen by ulHysteresis bytes.
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* pDeviceParams This contains either device specific data or a pointer to a
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* device specific structure containing additional information
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* not provided in this table.
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* ulCtrlPort1 This is the primary control port number for the device. This
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* may be used to specify different instances of the same device
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* type.
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* ulCtrlPort2 This is the secondary control port number, of use when a given
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* device has more than one available channel.
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* ulDataPort This is the port number for the data port of the device
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* ulIntVector This encodes the interrupt vector of the device.
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*
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*/
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console_tbl Console_Port_Tbl[] = {
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{
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"/dev/vga", /* sDeviceName */
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SERIAL_CUSTOM, /* deviceType */
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&i8042vga_fns, /* pDeviceFns */
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NULL, /* deviceProbe */
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NULL, /* pDeviceFlow */
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0, /* ulMargin */
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0, /* ulHysteresis */
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(void *)0, /* pDeviceParams */
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I8042_CS, /* ulCtrlPort1 */
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0, /* ulCtrlPort2 */
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I8042_DATA, /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_KBD /* ulIntVector */
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},
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{
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"/dev/com1", /* sDeviceName */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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NULL, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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16, /* ulMargin */
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8, /* ulHysteresis */
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(void *)9600, /* baud rate */ /* pDeviceParams */
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NS16550_PORT_A, /* ulCtrlPort1 */
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0, /* ulCtrlPort2 */
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NS16550_PORT_A, /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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PPCN_60X_IRQ_COM1 /* ulIntVector */
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},
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{
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"/dev/ser1", /* sDeviceName */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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80, /* ulMargin */
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8, /* ulHysteresis */
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(void *)9600, /* baud rate */ /* pDeviceParams */
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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1, /* Channel 1-4 */ /* ulDataPort */
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NULL, /* getRegister */
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NULL, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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},
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{
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"/dev/ser2", /* sDeviceName */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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80, /* ulMargin */
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8, /* ulHysteresis */
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(void *)9600, /* baud rate */ /* pDeviceParams */
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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2, /* Channel 1-4 */ /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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},
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{
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"/dev/ser3", /* sDeviceName */
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SERIAL_NS16550, /* deviceType */
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NS16550_FUNCTIONS, /* pDeviceFns */
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config_PMX1553_probe, /* deviceProbe */
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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96, /* ulMargin */
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8, /* ulHysteresis */
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(void *)57600, /* baud rate */ /* pDeviceParams */
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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3, /* Channel 1-4 */ /* ulDataPort */
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Read_ns16550_register, /* getRegister */
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Write_ns16550_register, /* setRegister */
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NULL, /* getData */
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NULL, /* setData */
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0, /* ulClock */
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| 185 |
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},
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{
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| 187 |
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"/dev/ser4", /* sDeviceName */
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SERIAL_NS16550, /* deviceType */
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| 189 |
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NS16550_FUNCTIONS, /* pDeviceFns */
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| 190 |
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config_PMX1553_probe, /* deviceProbe */
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| 191 |
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
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| 192 |
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96, /* ulMargin */
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| 193 |
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8, /* ulHysteresis */
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| 194 |
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(void *)57600, /* baud rate */ /* pDeviceParams */
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| 195 |
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PMX1553_BUS, /* PCI bus */ /* ulCtrlPort1 */
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PMX1553_SLOT, /* PCI slot */ /* ulCtrlPort2 */
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| 197 |
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4, /* Channel 1-4 */ /* ulDataPort */
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| 198 |
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Read_ns16550_register, /* getRegister */
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| 199 |
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Write_ns16550_register, /* setRegister */
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| 200 |
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NULL, /* getData */
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NULL, /* setData */
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| 202 |
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0, /* ulClock */
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| 203 |
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| 204 |
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},
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#if !PPCN_60X_USE_DINK
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| 206 |
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{
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| 207 |
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"/dev/com2", /* sDeviceName */
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| 208 |
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SERIAL_NS16550, /* deviceType */
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| 209 |
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NS16550_FUNCTIONS, /* pDeviceFns */
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| 210 |
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NULL, /* deviceProbe */
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| 211 |
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&ns16550_flow_RTSCTS, /* pDeviceFlow */
|
| 212 |
|
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16, /* ulMargin */
|
| 213 |
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8, /* ulHysteresis */
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| 214 |
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(void *)9600, /* baud rate */ /* pDeviceParams */
|
| 215 |
|
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NS16550_PORT_B, /* ulCtrlPort1 */
|
| 216 |
|
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0, /* ulCtrlPort2 */
|
| 217 |
|
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NS16550_PORT_B, /* ulDataPort */
|
| 218 |
|
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Read_ns16550_register, /* getRegister */
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| 219 |
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Write_ns16550_register, /* setRegister */
|
| 220 |
|
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NULL, /* getData */
|
| 221 |
|
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NULL, /* setData */
|
| 222 |
|
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0, /* ulClock */
|
| 223 |
|
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PPCN_60X_IRQ_COM2 /* ulIntVector */
|
| 224 |
|
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},
|
| 225 |
|
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#endif
|
| 226 |
|
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{
|
| 227 |
|
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"/dev/com3", /* sDeviceName */
|
| 228 |
|
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SERIAL_Z85C30, /* deviceType */
|
| 229 |
|
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Z85C30_FUNCTIONS, /* pDeviceFns */
|
| 230 |
|
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config_z85c30_probe, /* deviceProbe */
|
| 231 |
|
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&z85c30_flow_RTSCTS, /* pDeviceFlow */
|
| 232 |
|
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16, /* ulMargin */
|
| 233 |
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8, /* ulHysteresis */
|
| 234 |
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(void *)9600, /* baud rate */ /* pDeviceParams */
|
| 235 |
|
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Z85C30_CTRL_A, /* ulCtrlPort1 */
|
| 236 |
|
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Z85C30_CTRL_A, /* ulCtrlPort2 */
|
| 237 |
|
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Z85C30_DATA_A, /* ulDataPort */
|
| 238 |
|
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Read_85c30_register, /* getRegister */
|
| 239 |
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Write_85c30_register, /* setRegister */
|
| 240 |
|
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Read_85c30_data, /* getData */
|
| 241 |
|
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Write_85c30_data, /* setData */
|
| 242 |
|
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0, /* ulClock */
|
| 243 |
|
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PPCN_60X_IRQ_COM3_4 /* ulIntVector */
|
| 244 |
|
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},
|
| 245 |
|
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{
|
| 246 |
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"/dev/com4", /* sDeviceName */
|
| 247 |
|
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SERIAL_Z85C30, /* deviceType */
|
| 248 |
|
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Z85C30_FUNCTIONS, /* pDeviceFns */
|
| 249 |
|
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config_z85c30_probe, /* deviceProbe */
|
| 250 |
|
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&z85c30_flow_RTSCTS, /* pDeviceFlow */
|
| 251 |
|
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16, /* ulMargin */
|
| 252 |
|
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8, /* ulHysteresis */
|
| 253 |
|
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(void *)9600, /* baud rate */ /* pDeviceParams */
|
| 254 |
|
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Z85C30_CTRL_B, /* ulCtrlPort1 */
|
| 255 |
|
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Z85C30_CTRL_A, /* ulCtrlPort2 */
|
| 256 |
|
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Z85C30_DATA_B, /* ulDataPort */
|
| 257 |
|
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Read_85c30_register, /* getRegister */
|
| 258 |
|
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Write_85c30_register, /* setRegister */
|
| 259 |
|
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Read_85c30_data, /* getData */
|
| 260 |
|
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Write_85c30_data, /* setData */
|
| 261 |
|
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0, /* ulClock */
|
| 262 |
|
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PPCN_60X_IRQ_COM3_4 /* ulIntVector */
|
| 263 |
|
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}
|
| 264 |
|
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};
|
| 265 |
|
|
|
| 266 |
|
|
/*
|
| 267 |
|
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* Define serial port write registers structure.
|
| 268 |
|
|
*/
|
| 269 |
|
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typedef volatile struct _SP_WRITE_REGISTERS {
|
| 270 |
|
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unsigned char TransmitBuffer;
|
| 271 |
|
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unsigned char InterruptEnable;
|
| 272 |
|
|
unsigned char FifoControl;
|
| 273 |
|
|
unsigned char LineControl;
|
| 274 |
|
|
unsigned char ModemControl;
|
| 275 |
|
|
unsigned char Reserved1;
|
| 276 |
|
|
unsigned char ModemStatus;
|
| 277 |
|
|
unsigned char ScratchPad;
|
| 278 |
|
|
} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS;
|
| 279 |
|
|
|
| 280 |
|
|
static boolean config_PMX1553_probe(int minor)
|
| 281 |
|
|
{
|
| 282 |
|
|
unsigned8 ucBusNumber, ucSlotNumber, ucChannel;
|
| 283 |
|
|
unsigned8 ucIntLine;
|
| 284 |
|
|
unsigned32 ulPortBase, ulMemBase, ulDeviceID;
|
| 285 |
|
|
unsigned8 *pucSIO_cir, *pucUart_int_sr, *pucUartDevIntReg;
|
| 286 |
|
|
PSP_WRITE_REGISTERS pNS16550Write;
|
| 287 |
|
|
|
| 288 |
|
|
/*
|
| 289 |
|
|
* Extract PCI bus/slot and channel number
|
| 290 |
|
|
*/
|
| 291 |
|
|
ucBusNumber=Console_Port_Tbl[minor].ulCtrlPort1;
|
| 292 |
|
|
ucSlotNumber=Console_Port_Tbl[minor].ulCtrlPort2;
|
| 293 |
|
|
ucChannel=Console_Port_Tbl[minor].ulDataPort;
|
| 294 |
|
|
|
| 295 |
|
|
PCIConfigRead32(ucBusNumber,
|
| 296 |
|
|
ucSlotNumber,
|
| 297 |
|
|
0,
|
| 298 |
|
|
PCI_CONFIG_VENDOR_LOW,
|
| 299 |
|
|
&ulDeviceID);
|
| 300 |
|
|
|
| 301 |
|
|
if(ulDeviceID!=0x000111b5)
|
| 302 |
|
|
{
|
| 303 |
|
|
return FALSE;
|
| 304 |
|
|
}
|
| 305 |
|
|
|
| 306 |
|
|
/*
|
| 307 |
|
|
* At this point we know we have a PMC1553 or PMX1553 card
|
| 308 |
|
|
*
|
| 309 |
|
|
* Check for PMX1553 uart legacy IO ports
|
| 310 |
|
|
*/
|
| 311 |
|
|
PCIConfigRead32(ucBusNumber,
|
| 312 |
|
|
ucSlotNumber,
|
| 313 |
|
|
0,
|
| 314 |
|
|
PCI_CONFIG_BAR_3,
|
| 315 |
|
|
&ulPortBase);
|
| 316 |
|
|
|
| 317 |
|
|
if(ulPortBase==0)
|
| 318 |
|
|
{
|
| 319 |
|
|
/*
|
| 320 |
|
|
* This is either a PMC1553 or we can't see the uart
|
| 321 |
|
|
* registers
|
| 322 |
|
|
*/
|
| 323 |
|
|
return FALSE;
|
| 324 |
|
|
}
|
| 325 |
|
|
|
| 326 |
|
|
PCIConfigRead32(ucBusNumber,
|
| 327 |
|
|
ucSlotNumber,
|
| 328 |
|
|
0,
|
| 329 |
|
|
PCI_CONFIG_BAR_2,
|
| 330 |
|
|
&ulMemBase);
|
| 331 |
|
|
|
| 332 |
|
|
pucUartDevIntReg=(unsigned8 *)(PCI_MEM_BASE+ulMemBase);
|
| 333 |
|
|
pucUart_int_sr=(unsigned8 *)(PCI_MEM_BASE+ulMemBase+0x10);
|
| 334 |
|
|
pucSIO_cir=(unsigned8 *)(PCI_MEM_BASE+ulMemBase+0x18);
|
| 335 |
|
|
|
| 336 |
|
|
/*
|
| 337 |
|
|
* Use ulIntVector field to select RS232/RS422
|
| 338 |
|
|
*/
|
| 339 |
|
|
if(Console_Port_Tbl[minor].ulIntVector==0)
|
| 340 |
|
|
{
|
| 341 |
|
|
/*
|
| 342 |
|
|
* Select RS232 mode
|
| 343 |
|
|
*/
|
| 344 |
|
|
*pucSIO_cir&=~(1<<(ucChannel-1));
|
| 345 |
|
|
}
|
| 346 |
|
|
else
|
| 347 |
|
|
{
|
| 348 |
|
|
/*
|
| 349 |
|
|
* Select RS422 mode
|
| 350 |
|
|
*/
|
| 351 |
|
|
*pucSIO_cir|=1<<(ucChannel-1);
|
| 352 |
|
|
}
|
| 353 |
|
|
EIEIO;
|
| 354 |
|
|
/*
|
| 355 |
|
|
* Bring device out of reset
|
| 356 |
|
|
*/
|
| 357 |
|
|
*pucSIO_cir&=0xbf;
|
| 358 |
|
|
EIEIO;
|
| 359 |
|
|
/*
|
| 360 |
|
|
* Enable all channels as active
|
| 361 |
|
|
*/
|
| 362 |
|
|
*pucSIO_cir|=0x10;
|
| 363 |
|
|
EIEIO;
|
| 364 |
|
|
*pucSIO_cir&=0xdf;
|
| 365 |
|
|
|
| 366 |
|
|
PCIConfigRead8(ucBusNumber,
|
| 367 |
|
|
ucSlotNumber,
|
| 368 |
|
|
0,
|
| 369 |
|
|
PCI_CONFIG_INTERRUPTLINE,
|
| 370 |
|
|
&ucIntLine);
|
| 371 |
|
|
|
| 372 |
|
|
ulPortBase&=~PCI_ADDRESS_IO_SPACE;
|
| 373 |
|
|
|
| 374 |
|
|
ulPortBase+=8*(ucChannel-1);
|
| 375 |
|
|
|
| 376 |
|
|
Console_Port_Tbl[minor].ulCtrlPort1=
|
| 377 |
|
|
Console_Port_Tbl[minor].ulDataPort=ulPortBase;
|
| 378 |
|
|
if(Console_Port_Tbl[minor].pDeviceFns!=&ns16550_fns_polled)
|
| 379 |
|
|
{
|
| 380 |
|
|
Console_Port_Tbl[minor].ulIntVector=PPCN_60X_IRQ_PCI(ucIntLine);
|
| 381 |
|
|
|
| 382 |
|
|
/*
|
| 383 |
|
|
* Enable interrupt
|
| 384 |
|
|
*/
|
| 385 |
|
|
*pucUart_int_sr=(~*pucUart_int_sr)&(0x08<<ucChannel);
|
| 386 |
|
|
|
| 387 |
|
|
/*
|
| 388 |
|
|
* Enable interrupt to PCI
|
| 389 |
|
|
*/
|
| 390 |
|
|
*pucUartDevIntReg=(~*pucUartDevIntReg)&0x80;
|
| 391 |
|
|
}
|
| 392 |
|
|
else
|
| 393 |
|
|
{
|
| 394 |
|
|
/*
|
| 395 |
|
|
* Disable interrupt
|
| 396 |
|
|
*/
|
| 397 |
|
|
*pucUart_int_sr&=(0x08<<ucChannel);
|
| 398 |
|
|
}
|
| 399 |
|
|
|
| 400 |
|
|
/*
|
| 401 |
|
|
* Enable Auto CTS to facilitate flow control
|
| 402 |
|
|
*/
|
| 403 |
|
|
pNS16550Write=(PSP_WRITE_REGISTERS)Console_Port_Tbl[minor].ulCtrlPort1;
|
| 404 |
|
|
/*
|
| 405 |
|
|
* Enable special register set and unlock Enhanced Feature Register
|
| 406 |
|
|
*/
|
| 407 |
|
|
outport_byte(&pNS16550Write->LineControl, 0xbf);
|
| 408 |
|
|
/*
|
| 409 |
|
|
* Unlock enhanced function bits
|
| 410 |
|
|
*/
|
| 411 |
|
|
outport_byte(&pNS16550Write->FifoControl, 0x10);
|
| 412 |
|
|
/*
|
| 413 |
|
|
* Disable special register set and lock Enhanced Feature Register
|
| 414 |
|
|
*/
|
| 415 |
|
|
outport_byte(&pNS16550Write->LineControl, 0);
|
| 416 |
|
|
/*
|
| 417 |
|
|
* Select div 1
|
| 418 |
|
|
*/
|
| 419 |
|
|
outport_byte(&pNS16550Write->ModemControl, 0x00);
|
| 420 |
|
|
/*
|
| 421 |
|
|
* Enable special register set and unlock Enhanced Feature Register
|
| 422 |
|
|
*/
|
| 423 |
|
|
outport_byte(&pNS16550Write->LineControl, 0xbf);
|
| 424 |
|
|
/*
|
| 425 |
|
|
* Lock enhanced function bits and enable auto CTS
|
| 426 |
|
|
*/
|
| 427 |
|
|
outport_byte(&pNS16550Write->FifoControl, 0x80);
|
| 428 |
|
|
/*
|
| 429 |
|
|
* Disable special register set and lock Enhanced Feature Register
|
| 430 |
|
|
*/
|
| 431 |
|
|
outport_byte(&pNS16550Write->LineControl, 0);
|
| 432 |
|
|
|
| 433 |
|
|
/*
|
| 434 |
|
|
* The PMX1553 currently uses a 16 MHz clock rather than the
|
| 435 |
|
|
* 7.3728 MHz clock described in the ST16C654 data sheet. When
|
| 436 |
|
|
* available, 22.1184 MHz will be used allowing rates up to
|
| 437 |
|
|
* 1382400 baud (RS422 only).
|
| 438 |
|
|
*/
|
| 439 |
|
|
#if 1
|
| 440 |
|
|
/*
|
| 441 |
|
|
* Scale requested baud rate for 16 MHz clock
|
| 442 |
|
|
*/
|
| 443 |
|
|
(unsigned32)Console_Port_Tbl[minor].pDeviceParams*=7373;
|
| 444 |
|
|
(unsigned32)Console_Port_Tbl[minor].pDeviceParams/=16000;
|
| 445 |
|
|
#else
|
| 446 |
|
|
/*
|
| 447 |
|
|
* Scale requested baud rate for 22.1184 MHz clock
|
| 448 |
|
|
*/
|
| 449 |
|
|
(unsigned32)Console_Port_Tbl[minor].pDeviceParams/=3;
|
| 450 |
|
|
#endif
|
| 451 |
|
|
/*
|
| 452 |
|
|
* In order to maintain maximum data rate accuracy, we will
|
| 453 |
|
|
* apply a div 4 here rather than in hardware (using MCR bit 7).
|
| 454 |
|
|
*/
|
| 455 |
|
|
(unsigned32)Console_Port_Tbl[minor].pDeviceParams/=4;
|
| 456 |
|
|
|
| 457 |
|
|
return(TRUE);
|
| 458 |
|
|
}
|
| 459 |
|
|
|
| 460 |
|
|
static boolean config_z85c30_probe(int minor)
|
| 461 |
|
|
{
|
| 462 |
|
|
/*
|
| 463 |
|
|
* PPC1 and PPC1a do not have this device
|
| 464 |
|
|
*/
|
| 465 |
|
|
if((ucSystemType==SYS_TYPE_PPC1) ||
|
| 466 |
|
|
(ucSystemType==SYS_TYPE_PPC1a))
|
| 467 |
|
|
{
|
| 468 |
|
|
return (FALSE);
|
| 469 |
|
|
}
|
| 470 |
|
|
|
| 471 |
|
|
/*
|
| 472 |
|
|
* All other boards supported by this BSP have the z85c30 device
|
| 473 |
|
|
*/
|
| 474 |
|
|
|
| 475 |
|
|
/*
|
| 476 |
|
|
* Ensure that CIO port B is configured for
|
| 477 |
|
|
* default driver enable
|
| 478 |
|
|
*/
|
| 479 |
|
|
outport_byte(0x861, 0x33);
|
| 480 |
|
|
|
| 481 |
|
|
return(TRUE);
|
| 482 |
|
|
}
|
| 483 |
|
|
|
