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/*
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* COPYRIGHT (c) 1998 by Radstone Technology
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*
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*
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* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
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* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
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* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
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*
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* You are hereby granted permission to use, copy, modify, and distribute
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* this file, provided that this notice, plus the above copyright notice
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* and disclaimer, appears in all copies. Radstone Technology will provide
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* no support for this code.
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*
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*/
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/*
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* Definitions for the mk48t18 RTC/NvRAM
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*/
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#ifndef _MK48T18_H
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#define _MK48T18_H
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#include "prepnvr.h"
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/*
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* This structure maps to the top of the NvRAM. It is based on the standard
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* CMOS.h file for the ds1385. Feature and system dependant areas are preserved
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* for potential compatibility issues.
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*
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* The CRC's are computed with x**16+x**12+x**5 + 1 polynomial
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* The clock is kept in 24 hour BCD mode and should be set to UT(GMT)
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*/
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typedef struct _MK48T18_CMOS_MAP {
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unsigned8 SystemDependentArea2[8];
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unsigned8 FeatureByte0[1];
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unsigned8 FeatureByte1[1];
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unsigned8 Century; /* century byte in BCD */
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unsigned8 FeatureByte3[1];
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unsigned8 FeatureByte4[1];
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unsigned8 FeatureByte5[1];
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unsigned8 FeatureByte6[1];
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unsigned8 FeatureByte7[1];
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unsigned8 BootPW[14];
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rtems_unsigned16 BootCrc; /* CRC on BootPW */
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unsigned8 ConfigPW[14];
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rtems_unsigned16 ConfigCrc; /* CRC on ConfigPW */
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unsigned8 SystemDependentArea1[8];
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/*
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* The following are the RTC registers
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*/
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volatile unsigned8 Control;
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volatile unsigned8 Second:7; /* 0-59 */
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volatile unsigned8 Stop:1;
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volatile unsigned8 Minute; /* 0-59 */
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volatile unsigned8 Hour; /* 0-23 */
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volatile unsigned8 Day:3; /* 1-7 */
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volatile unsigned8 Resvd1:3; /* 0 */
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volatile unsigned8 FT:1; /* Frequency test bit - must be 0 */
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volatile unsigned8 Resvd2:1; /* 0 */
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volatile unsigned8 Date; /* 1-31 */
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volatile unsigned8 Month; /* 1-12 */
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volatile unsigned8 Year; /* 0-99 */
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} MK48T18_CMOS_MAP, *PMK48T18_CMOS_MAP;
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/*
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* Control register definitions
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*/
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#define MK48T18_CTRL_WRITE 0x80
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#define MK48T18_CTRL_READ 0x40
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#define MK48T18_CTRL_SIGN 0x20
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#define MK48T18_NVSIZE 8192-sizeof(MK48T18_CMOS_MAP)
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#define MK48T18_GESIZE (MK48T18_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER))
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#define MK48T18_BASE (PMK48T18_NVRAM_MAP)((unsigned8 *)PCI_MEM_BASE+0x00800000)
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/* Here is the whole map of the MK48T18 NVRAM */
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typedef struct _MK48T18_NVRAM_MAP {
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HEADER Header;
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unsigned8 GEArea[MK48T18_GESIZE];
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unsigned8 OSArea[OSAREASIZE];
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unsigned8 ConfigArea[CONFSIZE];
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MK48T18_CMOS_MAP CMOS;
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} MK48T18_NVRAM_MAP, *PMK48T18_NVRAM_MAP;
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#endif /* _MK48T18_H */
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